NV50 specs?

[radar1200gs]

Once again I fail to see a problem.

DDR-1 signalling is a subset of DDR-2 signalling. Additionally the two memory types would live in different areas of the memory map. Pretty easy for the controller to know when to talk what protocol.

 

[Fodder]

Once again I fail to see a problem.

It's a problem of economic and engineering viability, not technical possibility. The extra pins, traces, pcb layers and jiggly bits inside the GPU start to add up in terms of space and cost.

 

[radar1200gs]

A reasonably simple solution might be to package the DDR-1 memory as if it were DDR-2 or GDDR-3 and then always address it it DDR-1 compatability mode (remember you know where on the memory map the DDR-1 is, so you can do this).

Because you are going to be building a high volume mainstream part, the cost of packaging the memory this way would be fairly negligible.

 

[incurable]

A reasonably simple solution might be to package the DDR-1 memory as if it were DDR-2 or GDDR-3 and then always address it it DDR-1 compatability mode (remember you know where on the memory map the DDR-1 is, so you can do this).

Do I understand you correctly if I think that you're proposing different ports of the same crossbar memory controller to interface with various types of DRAM at multiple speeds & latencies all at the same time, using busses that are in total no wider than comparable ('monolitic memory', if you will) mainstream GPU architectures?

cu

incurable :?

 

[radar1200gs]

I don't think you would be able to access different memory types in one cycle on the crossbar, but with a texture cache in the GDDR3, that should not be a huge problem.

 

[KimB]

I don't think you would be able to access different memory types in one cycle on the crossbar, but with a texture cache in the GDDR3, that should not be a huge problem.

I think that's the point. You'd totally destroy the whole purpose of striping data across the different chips and using a crossbar architecture in the first place.

With today's architectures, it is possible to dedicate the entire 256 bits of bandwidth (or whatever is available) per clock to z-buffer accesses, or color buffer accesses, or texture addresses.

 

[Tim]

Well I don't know about the Radeons but the 5700 supports GDDR3, DDR2 and DDR all off of the same chip so I doubt its quite the problem you are making it out to be.

You, can not use GDDR3, DDR2 and DDR at the same time with the 5700 (they share the same pins), if you wan't to use two memory types at once you need about twice the pins.

 

[kenneth9265_3]

How much of a difference is GDDR3 is going to make over GDDR3 or DDRII?

 

[radar1200gs]

I'll try one last time.

You should not require two different busses or different electrical signalling to use DDR-1 memory alongside DDR-II memory when it is packaged as though it were DDR-II.

DDR-II modules can be accessed in a DDR-1 compatability mode (go to JEDEC and read the DRR-II spec). ATi knows all about this mode since its what it used to "demonstrate" a "DDR-II capable" R300 on Tech-tv prior to NV30's launch...

To use this feature of DDR-II for cost cutting all you need to do is have the GPU memory controller address RAM at a certain point in the memory space in DDR-1 compatability mode rather than DDR-2 mode. The physical connections, routes etc on the board are exactly the same as for full blown DDR-II

 

[stepz]

But there's no point in doing that because even if you get the efficency up to the same level as a symmetric solution (very very difficult) there is no cost savings in it. Making half of the chips twice as fast costs about the same if not more as making all the chips 1.5 times faster, but the development costs will go way up, because you need to balance the bandwidth between different chips/channels for it to be useful (as opposed to selecting the channel by the 7th and 8th bit of the memory address).

 

[radar1200gs]

You are forgetting this would be a mainstream product sold in very large quantities over a fairly long period of time. Economies of scale resulting from that will more than offset the (slight) development costs.

 

[KimB]

I'll try one last time.

You should not require two different busses or different electrical signalling to use DDR-1 memory alongside DDR-II memory when it is packaged as though it were DDR-II.

DDR-II modules can be accessed in a DDR-1 compatability mode (go to JEDEC and read the DRR-II spec). ATi knows all about this mode since its what it used to "demonstrate" a "DDR-II capable" R300 on Tech-tv prior to NV30's launch...

It still wouldn't work. You're forgetting that data is striped across all chips, and splitting data up to specific chips will lower performance. The setup you describe would be higher-perfroming in DDR-1 only mode.

 

[Tim Murray]

Ah, latencies. We all forget about latencies on video card memory, but they're there, always watching us, waiting for the right time to strike.

Case in point--the 5900 to 5950 Ultra BIOS flash. In some cases, slightly higher memory clocks, but slightly lower memory performance. HOW COULD THIS BE? Latencies. They're Evil!

 

[Sazar]

Ah, latencies. We all forget about latencies on video card memory, but they're there, always watching us, waiting for the right time to strike.

Case in point--the 5900 to 5950 Ultra BIOS flash. In some cases, slightly higher memory clocks, but slightly lower memory performance. HOW COULD THIS BE? Latencies. They're Evil!

say it isn't so

btw... what news of SOI for ati's next next-gen cards? post r420?

low-k gonna be all the invest in or is there a soi implementation in the near future?

also... liklihood of either of the big ihv's using strained silicon?

 

[stepz]

You are forgetting this would be a mainstream product sold in very large quantities over a fairly long period of time. Economies of scale resulting from that will more than offset the (slight) development costs.

Just by making a portion of the memory channels faster will buy at most a marginal performance increase, if any. Data must be arranged on the chips so that faster channels will see proportinally larger amount of accesses averaged over a relatively small time window. That is several orders more difficult than just interleaving the data for pixels in a quad over avilable channels. Even if a generally applicable solution is possible within a given transistor and timing budget there just isn't any point because the performance gain per $ is at most negligible.
You will just be making a product that has the same performance for the per unit cost, but with added development cost.

 

[kenneth9265_3]

Now that the NV40 reviews are out, do the majority still think that the NV50 will be a bigger leap in technology over the NV40 than the NV40 was over the NV30? :?

 

[jimmyjames123]

Now, I'd bet that most of us are even more convinced that the leap from NV40 to NV50 will be more revolutionary.

The NV40 looks like NVDA's attempt to make a super fast, fairly futureproof card that has distinct lines drawn regarding what it can and can't do. What the NV40 is designed to do, it does exceptionally well, but it is not attempting to hit the ball out of the ballpark in all arenas.

NV40 is a great product for NVDA because it will bring interest back from high-end gamers and developers who are interested in working with the new and exciting graphics technology. This is setting the stage for the NV50...

With the NV50, I would think that we should expect significantly higher image quality for both AF and AA, with higher framerates too. Process improvements should help quite a bit too.

 

[Megadrive1988]

I will not attempt to speculation on what revolutionary features NV50 will or will not have. I'll just focus on brute processing strength since that is much easier 8)

still betting on 32 pixel pipelines with at least 12 Vertex Shaders
(NV40 has 16 and 6 respectively) and a 600 Mhz core clock.

Nvidia *will* break the 10 gigapixels/sec fillrate barrier as well as the 1 billion verts/sec barrier with NV50

 

[Megadrive1988]

NV50 predictions based on what's in NV40

90 nm / 0.90 micron
400~450 million transistors
32-pipes
12 vertex shaders
Shader Model 4.0 +
500 Mhz core
16 gigapixel / sec
1.2 billion + vertices / sec

alternatively, we might have 16 pipes, but they "double the math" again over NV40, with more pixel shader units, or whatever that was they did.

then you can clock it to something like 700 Mhz and still get over 10 gigapixels of fillrate

 

[ChronoReverse]

~400-450 million transistors...