kid_crisis
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LeStoffer said:Hmmm, I think that this speculation by the News Editor at Semiconductor Fabtech has been mentioned before, but here we go again about the low k nightmare:
The NV30 graphics chip was planned to be launched using TSMC’s 130nm copper and CVD based low k dielectric process. This would have been the first chip tape out for volume production using the most advanced foundry process currently available. RussSchultz, if the process is broken how can you fix it by tweaking your silicon?
Edit: I ask because TCMS have a less advanced but nice working .13 process on less complex chip designs.
About 2.5 months ago Jen Hsun claimed that they would not be using low-k dielectrics on the NV30 design. He did not elaborate on the statement though (i.e. did they originally plan to use low-k and then had to "fallback" to a no-low-k approach?) So if they are seeing more problems in the 0.13um process on NV30, it's probably not due to low-k dielectrics. The other big problem that foundries were having was voids in the copper interconnects that caused broken connections when temperature cycled, i.e. in reliability testing. That isn't something that would probably be known halfway through a processing run though (which is presumably where NV30 is right now, I guess).