NV to leave IBM?
- Thread starter Tim Murray
- Start date
Ouch. If that news is true about TSMC then the whole industry will be hurtin till things get worked out. =(
Didn't Nvidia leave TSMC only recently for IBM? Wonder if this will affect NV40's retail availability. Although then again if TSMC is having problems I guess they'd have been screwed either way. Who does ATI use anyway?
Didn't Nvidia leave TSMC only recently for IBM? Wonder if this will affect NV40's retail availability. Although then again if TSMC is having problems I guess they'd have been screwed either way. Who does ATI use anyway?
radar1200gs
Regular
Sounds like sour grapes on the part of the Tiawanese foundries to me.
As already pointed out, TSMC is overbooked already, so who will do the fabbing.
IIRC there were rumors spreading just after NV38 launched that nVidia and IBM were going to split, because IBM had better customers or some such tosh. Obviously that never happened either.
As already pointed out, TSMC is overbooked already, so who will do the fabbing.
IIRC there were rumors spreading just after NV38 launched that nVidia and IBM were going to split, because IBM had better customers or some such tosh. Obviously that never happened either.
radar1200gs
Regular
NV38, NV36 & NV40 are all fabbed by IBM.
NV34 is the only GPU currently being fabbed for nVidia by TSMC.
(EDIT: TSMC does GF4 MX also FWIW).
NV34 is the only GPU currently being fabbed for nVidia by TSMC.
(EDIT: TSMC does GF4 MX also FWIW).
Doomtrooper
Veteran
TSMC has been booked solid for a while, ATI has been increasing orders and the X-box 2 partnership between TSMC and M$ has also increased the load.
http://www.digitimes.com/NewsShow/Article2.asp?datePublish=2004/04/15&pages=A2&seq=6
http://news.com.com/2100-1040_3-5185492.html?tag=cd.lede
http://www.digitimes.com/NewsShow/Article2.asp?datePublish=2004/04/15&pages=A2&seq=6
http://news.com.com/2100-1040_3-5185492.html?tag=cd.lede
Does the number of metal layers make any difference? Or are you just looking for trivia?
radar1200gs
Regular
The number of metal layer interconnects can make a difference, AMD usually increases the metal layer count by one between model revisions (K7 > Thunderbird > Palomino > Thoroughbred > Barton). It increases clockability but also complexity.
I haven't heard the number of layers NV40 uses. To the best of my knowlege NV40 does not use SOI. SOI is mainly where IBM is experiencing its yield difficulties.
I haven't heard the number of layers NV40 uses. To the best of my knowlege NV40 does not use SOI. SOI is mainly where IBM is experiencing its yield difficulties.
Megadrive1988
Veteran
makes no sense to me. I don't understand.
I thought NV40 fabbed by IBM was a relatively painless experience for Nvida, compared to TSMC fabbing NV30.
I thought NV40 fabbed by IBM was a relatively painless experience for Nvida, compared to TSMC fabbing NV30.
I think it was on this board that someone mentioned that NV said that IBM was the "ONE" fab for NV???
And if the article is true (who knows?) Then where will they go? Doesn't NV have to see how the chip turns out on a new FAB before just redirecting all the work to the new FAB?
And if the article is true (who knows?) Then where will they go? Doesn't NV have to see how the chip turns out on a new FAB before just redirecting all the work to the new FAB?
radar1200gs
Regular
Megadrive:
It was painless compared to TSMC. Look at nVidia's former cores from TSMC. Most of them required at least 3 respins before being released to production (GF3 was A4 at release). NV40 is going to be released on A1 or A2 silicon (NV38 & NV36 were just as good). That saves a lot of money and time.
Unit01:
Its too late for nVidia to go anywhere until nV45 at the moment even if they wanted to. NV30 was fabbed in TSMC despite the problems, wasn't until NV35 that nVidia shifted fabs (unless nVidia taped NV40 out at IBM & TSMC concurrently, but TSMC has no capacity).
It was painless compared to TSMC. Look at nVidia's former cores from TSMC. Most of them required at least 3 respins before being released to production (GF3 was A4 at release). NV40 is going to be released on A1 or A2 silicon (NV38 & NV36 were just as good). That saves a lot of money and time.
Unit01:
Its too late for nVidia to go anywhere until nV45 at the moment even if they wanted to. NV30 was fabbed in TSMC despite the problems, wasn't until NV35 that nVidia shifted fabs (unless nVidia taped NV40 out at IBM & TSMC concurrently, but TSMC has no capacity).
Doomtrooper
Veteran
Megadrive1988 said:
I doubt a ASIC of this complexity would be painless in any way, If IBM lost 150 million dollars then I would say IBM is the one that is feeling the heat.
@Russ Schultz
Interconnect Layers are really important when it comes to yields,
therefore costs and line speed in a FAB, means production time.
AMD uses now 9 interconnect layers with K8 on SOI which is the
highest number so far. Intel is using 6 Layers and is now going to
8 also on 130nm which got an update - you know 90nm went very
bad for them so far ...
AMD increased the interconnect layers at the Tbred from A to the
B Step from 6 to 8 and could increase the BIN's by a huge amount.
Try to view this as a circuit redesign in which the critical paths got
worked out, so that the core could run at higher speed. Think of
path (lenghts) as a real waylenght which could be now way shorter, when
you add interconnect layers, but it gets here really complicate.
These are no easy and fast modifications.
So my indication was to get a feeling what NVDA is now doing at
Fishkill and at which process. Funny, that Apple (IBM with PPC) has
big problems to get PPC's at 90nm. So I guess, that NVDA wanted
to build also on 90nm and realized, that IBM is not ready right now
and therefore goes first time crazy on 130nm with a 300mm^2 design.
Men, the guys have big nerves, that design is REALLY EXPENSIVE!!!
BUGGI
Interconnect Layers are really important when it comes to yields,
therefore costs and line speed in a FAB, means production time.
AMD uses now 9 interconnect layers with K8 on SOI which is the
highest number so far. Intel is using 6 Layers and is now going to
8 also on 130nm which got an update - you know 90nm went very
bad for them so far ...
AMD increased the interconnect layers at the Tbred from A to the
B Step from 6 to 8 and could increase the BIN's by a huge amount.
Try to view this as a circuit redesign in which the critical paths got
worked out, so that the core could run at higher speed. Think of
path (lenghts) as a real waylenght which could be now way shorter, when
you add interconnect layers, but it gets here really complicate.
These are no easy and fast modifications.
So my indication was to get a feeling what NVDA is now doing at
Fishkill and at which process. Funny, that Apple (IBM with PPC) has
big problems to get PPC's at 90nm. So I guess, that NVDA wanted
to build also on 90nm and realized, that IBM is not ready right now
and therefore goes first time crazy on 130nm with a 300mm^2 design.
Men, the guys have big nerves, that design is REALLY EXPENSIVE!!!
BUGGI
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