you can take a look at current handhelds, batteries wont improve much. In the case of the PSP you are looking at a 2000mAh Accu, which lasts 4-6 hours, meaning the whole PSP (LCD,2xMIPS CPU, Gfx Chip, RAM) draws less then 0.5 Watt. Should give you an idea how much you can spend on 1 CPU.. it aint much and I cant see anything but MIPS or ARM fitting the bill (both beeing way leaner then PPC btw). 1-2 cutdown SPEs might be possible, but I doubt it.
And if you think there will be whole cores (out of 2-3 available) sucking power while beeing locked away for the OS, then you are nuts
Ahem... how much interaction do you think devs have with the Media Engine and its friends on the current PSP (we are talking about a several GOPS capable configurable sound processor [the VME], a video decoding engine, and a full MIPS R4000i+FPU core... all locked away for the OS)
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Here I am talking about a single SPE doing ALL of that (video decoding, sound processing, DRM, OS assistance, etc...).
Also >=0.5 Watts might well be achievable... a 2200 mAh battery for the current PSP is already out now
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Sure, low voltage is key... right now the current 45 nm CELL BE can reach 3.2 GHz with a Vdd of 0.9V and sucking out about 20 Watts... and we are talking about full good ol' PPE (which is one of the hottest power hungry portions of the chip), 25.6 GB/s XDR MC, 35 GB/s FlexIO, full-speed and full-scale EIB, etc...
Replace the PPE with a very low power MIPS/ARM core, take out 4 SPE's, scale down or replace the EIB, re-do XDR MC and FlexIO interfaces to optimize them for low power operation (and different bandwidth requirements a portable platform would have given the performance it is targeting), and clock it all at 600 MHz (how low can they get the voltage to go? Not clear...)...
http://www.realworldtech.com/page.cfm?ArticleID=RWT022508002434&p=3 (and other pages in that same article)
I am not sure a 1/100th of the power consumption of the current CELL BE 45 nm at 3.2 GHz can be achieved (it would place it at 0.2 Watts) though...
We could also remove the FlexIO interface completely, if we were to keep a rectangular die for the processor and embed the GPU core in it.
An SPE is 6.47 mm^2 at 45 nm (at least in the version they showed at ISSCC 2008).
The largest (in this PR
http://findarticles.com/p/articles/mi_m0ECZ/is_2005_August_1/ai_n14844669 )
PowerVR SGX core is about 8 mm^2@90 nm so even considering a 45% scaling from 90 nm to 45 nm would net us 3.6 mm^2 (and everyone criticized SPE scaling from 90 nm to 45 nm because it "only" got a 43.9% scaling).
We could almost double that core and still kinda fit in the same space of a missing SPE...
CPU core + 2-3 SPE + ~6 mm^2 PowerVR SGX core all in the same die, clocked at 600 MHz and with the SGX core clocked at 300 MHz or less (depending on the internal bus speed).
It should pack quite a bit of punch
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