New week...new CELL related patents :)

[nAo]

Ring-topology based multiprocessor data access bus

Symmetric multi-processing system

To be fair there are some other new patents by IBM related to high speed memory transfers in a multiprocessors system with shared memory ..but those don't appear to be connected with CELL architecture

ciao,
Marco

 

[nAo]

You lazy! I have to do all the work..

I just read the first patent (the second one doesn't seem to be interesing at all..). It depicts a PE with 8 APUs.
The APUs are connected to each other by a ring pipelined bus. This bus has a 576 data bus (which carry 512 bits data packets per clock). Commands data bus is 77 bits wide.
Small (8 Kbytes) local memories are attached to each APU to store data that have to be read/written on the ring data bus.
In a previous patent data bus clock was 2 Ghz..so the data bandwith of this bus would be something in the order of 128 Gigabytes/s per PE.
IIRC in another patent shared dram could provide 1024 bits words per data bus clock cycle. If this hold true the shared dram could sustain at most 2 PE with a 1:1 bandwith ratio. But it has to be noted that a PU can inject data in the ring bus also via its L2 cache..

ciao,
Marco

 

[London Geezer]

Soccia,
Is it me or does it all seem a bit unbalanced? Looks like the BE will be sit there waiting for the RAM to send data to it for quite a long time... Which is what has been happening ever since RAM was born, so it's not too bad really.

 

[Fafalada]

It's not that I'm lazy, I just got to this thread like minutes before your second post...

Anyway, point of interest (ERP voiced concerns over this mostly, but we all shared them really) - there actually IS L2 cache on the PE. Granted we still don't know configuration or size of it...

A minor annoyance - they speak of possible dual and single ported APU memory in the same freaking paragraph, how is one supposed to decide which is more likely

 

[nAo]

Soccia,
Is it me or does it all seem a bit unbalanced? Looks like the BE will be sit there waiting for the RAM to send data to it for quite a long time... Which is what has been happening ever since RAM was born, so it's not too bad really.

No..not in the general case. as I pointed out data injected in the ring bus are not coming just from shared dram..there is also the PU's L2 cache.
And APUs can obviously write data in the ring bus too!

 

[Panajev2001a]

Ring-topology based multiprocessor data access bus

Symmetric multi-processing system

To be fair there are some other new patents by IBM related to high speed memory transfers in a multiprocessors system with shared memory ..but those don't appear to be connected with CELL architecture

ciao,
Marco

The second patent is a followup ( even though it does not have IBM as assignee name, not like we really need to read that... ) of this patent Symmetric multi-processing system_old

The biggest change is this section that was added:

[0013] It would therefore be desirable to develop an SMP computer architecture where the APU's have restricted access to the shared memory without being structurally configured with an address translation mechanism. It would further be desirable to develop an SMP computer architecture where the APU's have more capabilities than prior art APU's, i.e., structured to perform a particular task. It would further be desirable to develop an SMP system where Translation Lookaside Buffer (TLB) consistency may be maintained by the processing units only.

 

[Guden Oden]

Is it me or does it all seem a bit unbalanced? Looks like the BE will be sit there waiting for the RAM to send data to it for quite a long time...

Well, no matter how you twist and turn, if you have 8APUs (and a PU, so sum total 9 processors) all connected via one bus, there's going to be inevitable data starvation if you make all of them access memory at the same time, there's no (realistic) way around it. Like in a supermarket, there aren't cash registers for every single customer that is finished with shopping and wants to leave, one has to wait in line.

HOPEFULLY though, the programming model will rather be to send data to one APU which starts chewing on it and then delivers it on to another APU which delivers it on to the next, all via this ring bus. If I understand what's been said, MORE than one PU can actually send data on this ring bus without disturbing the others, or locking up the 1024-bit bus coming from eDRAM.

That would be pretty damn cool if that was the case. Of course, it would be even cooler if the actual BB chip in the PS3 was implemented in such a manner too! Patents are one thing, and reality quite another I know.

 

[nAo]

Even in those patents is named the SPU..Synergistic APU.
I'm wondering if there are different type of APUs..let say..Graphics APU..a GPU

 

[nAo]

A minor annoyance - they speak of possible dual and single ported APU memory in the same freaking paragraph, how is one supposed to decide which is more likely

Sorry Faf..I can't find it..may you point me to that paragraph?

 

[thop]

A bit OT, but whats the best site to search for/through patents?

 

[nAo]

The most up to date: http://www.uspto.gov
But I prefer this: http://ep.espacenet.com

 

[Megadrive1988]

interesting.

I'd like Pana's and Faf's comments on this.

 

[MfA]

[0013] It would therefore be desirable to develop an SMP computer architecture where the APU's have restricted access to the shared memory without being structurally configured with an address translation mechanism. It would further be desirable to develop an SMP computer architecture where the APU's have more capabilities than prior art APU's, i.e., structured to perform a particular task. It would further be desirable to develop an SMP system where Translation Lookaside Buffer (TLB) consistency may be maintained by the processing units only.

Segment based MMUs such as the PowerPC has are uniquely suited to software address translation BTW.

 

[Pepto-Bismol]

Considering the sheer volume of technology patents IBM files each year, unscrambling the Cellular enigma will be like finding the preverbal needle in a haystack.

IBM generated the most U.S. patents in 2002, the tenth consecutive year that it led the world, according to figures released today by the United States Patent and Trademark Office.

IBM was awarded 3,288 patents, nearly doubling the output of the second most productive company.

In the past decade, IBM inventors have received a record 22,357 patents, besting the next closest company, Canon, by nearly 7,000 patents.

Source: Metropolitan Computer Times

 

[Panajev2001a]

Considering the sheer volume of technology patents IBM files each year, unscrambling the Cellular enigma will be like finding the preverbal needle in a haystack.

Yes, but this helps :

Most recently, Michael Gschwind was a member of IBM's 5 person technical contact team (with Jim Kahle, Chuck Moore, Marty Hopkins, Peter Hofstee) which jointly defined the CELL architecture with Sony and Toshiba. This work led to the establishment of the S/T/I design center in Austin, TX and was rated an IBM Research division accomplishment.

http://www.research.ibm.com/people/m/mikeg/

 

[Pepto-Bismol]

Yes, but this helps

It's trivia to most, but a lifesaver to the author or journalist who's just dying for an interview ...

Maybe, just maybe Dr. Gschwind, a former member of the Cell team (and former electrical engineering professor at Princeton University), might have been smart enough NOT to leave a paper trail ... well, an obvious one anyway.

In all likelihood, a synoptic description of Cell is strewn about several hundred patents, some of which have yet to be filed.