Paul and Others interested,
These are all the times *switch* is used in the last Sony patent.
[0063] The basic processing module for all members of network 104 is the processor element (PE). FIG. 2 illustrates the structure of a PE. As shown in this figure, PE 201 comprises a processing unit (PU) 203, a direct memory access controller (DMAC) 205 and a plurality of attached processing units (APUs), namely, APU 207, APU 209, APU 211, APU 213, APU 215, APU 217, APU 219 and APU 221. A local PE bus 223 transmits data and applications among the APUs, DMAC 205 and PU 203. Local PE bus 223 can have, e.g., a conventional architecture or be implemented as a packet switch network. Implementation as a packet switch network, while requiring more hardware, increases available bandwidth.
A Packet switch network is a router (*SERVER*) function. Where the data being handled needs minimal processing and maximal routing. The data packets are moved as efficiently as possible and switched to the fastest route (not always the shortest). Packet switch networks are mostly used by Telephone companies. They reduce previous bandwidth constraints to a fifth that presented by circuit-switched networks. However it would also facilitate Video On Demand (VOD) and other streaming services that Sony wants and demand endless bandwidth. To support this goal an internal company was formed called, Sony BroadBand Network (SBBN).
http://www.google.com/search?num=10...p;newwindow=1&q="Sony+Broadband+Network""
[0082] FIG. 12A illustrates the control system and structure for the DRAM of a BE. A similar control system and structure is employed in processors having other sizes and containing more or less PEs. As shown in this figure, a cross-bar switch connects each DMAC 1210 of the four PEs comprising BE 1201 to eight bank controls 1206. Each bank control 1206 controls eight banks 1208 (only four are shown in the figure) of DRAM 1204. DRAM 1204, therefore, comprises a total of sixty-four banks. In a preferred embodiment, DRAM 1204 has a capacity of 64 megabytes, and each bank has a capacity of 1 megabyte. The smallest addressable unit within each bank, in this preferred embodiment, is a block of 1024 bits.
To further clarify,
The unspecified DRAM consists of 64MB total, to shared by all four PE.
Not 64MB per PE as I understood you to be stating.
[0083] BE 1201 also includes switch unit 1212. Switch unit 1212 enables other APUs on BEs closely coupled to BE 1201 to access DRAM 1204. A second BE, therefore, can be closely coupled to a first BE, and each APU of each BE can address twice the number of memory locations normally accessible to an APU. The direct reading or writing of data from or to the DRAM of a first BE from or to the DRAM of a second BE can occur through a switch unit such as switch unit 1212.
Here it says that APU outside of the BE also have access to this Shared DRAM.
And that this is possible for closely coupled BE (Onboard? Server Cabinet?).
[0084] For example, as shown in FIG. 12B, to accomplish such writing, the APU of a first. BE, e.g., APU 1220 of BE 1222, issues a write command to a memory location of a DRAM of a second BE, e.g., DRAM 1228 of BE 1226 (rather than, as in the usual case, to DRAM 1224 of BE 1222). DMAC 1230 of BE 1222 sends the write command through cross-bar switch 1221 to bank control 1234, and bank control 1234 transmits the command to an external port 1232 connected to bank control 1234. DMAC 1238 of BE 1226 receives the write command and transfers this command to switch unit 1240 of BE 1226. Switch unit 1240 identifies the DRAM address contained in the write command and sends the data for storage in this address through bank control 1242 of BE 1226 to bank 1244 of DRAM 1228. Switch unit 1240, therefore, enables both DRAM 1224 and DRAM 1228 to function as a single memory space for the APUs of BE 1222.
This explains that APU of BE’s can communicate with each other via memory.
[0088] FIG. 16 shows an alternative embodiment of the DMAC, namely, a non-distributed architecture. In this case, the structural hardware of DMAC 1606 is centralized. APUs 1602 and PU 1604 communicate with DMAC 1606 via local PE bus 1607. DMAC 1606 is connected through a cross-bar switch to a bus 1608. Bus 1608 is connected to DRAM 1610
I don’t fully understand this one.
All the APU share a single connection to the DMAC.
Cross-bar switch to a bus. Is this bus a switched bus?
Anyways these are all the times that *Switch* is mentioned in the Patent.
At no time does it state the bit size of any switch.
Elsewhere is does say that the DMAC has a memory bank of 8KB.
It can buffer transfers as 1024bits or as 512 interleaved bits in two banks.
But it never says the bit size of a bus other than the main PE bus.
So we have no information on how many bits a DRAM bus might be.
[0086] FIGS. 14A and 14B illustrate different configurations for storing and accessing the smallest addressable memory unit of a DRAM, e.g., a block of 1024 bits. In FIG. 14A, DMAC 1402 stores in a single bank 1404 eight 1024 bit blocks 1406. In FIG. 14B, on the other hand, while DMAC 1412 reads and writes blocks of data containing 1024 bits, these blocks are interleaved between two banks, namely, bank 1414 and bank 1416. Each of these banks, therefore, contains sixteen blocks of data, and each block of data contains 512 bits. This interleaving can facilitate faster accessing of the DRAM and is useful in the processing of certain applications.
To sum things up.
If there is 64MB of eDRAM it is shared by the whole BroadBand Engine.
At no time is the bit size of a switch or DMAC but beyond the PE identified.
The word “switch†first occurs in relation to a packet switch network.
Which is a term generally applied to routing operations hubs or servers.
To me all of this reads *server* related.
Help review the following,
[0088] You don’t need a distributed DMAC in a packet switching network.
The only time a switch to a bus happens is in this alternative design where the DMAC is not distributed in the PE. Since internal processing is minimal they can take turns returning the data and do not have to compete for memory requests in order to continue processing.
So this is the only mention of switch and bus. Is it a packet network example?
Quote and link.