New IBM patents, CELL related(?)

[nAo]

I just found some new patents applications that I believe can be related to CELL development.
IMHO, the most interesting are this first couple of patents:

Multiphase clocking method and apparatus
Microprocessor chip simultaneous switching current reduction method and apparatus

They describe how to distribuite power requirements in a PE in space and time. There is a base clock running a 1 GHz, that is multiplied to produce a 2 GHz clock for the DMA Controller and a 4 GHz clock for each APU.
The clock is distribuited and skewed in a way each unit work desynched from a fixed amount of time from any other unit.
There is also a ring net that connects DMAC to APUs.
These patents describe a scenario where a single CPU is attached to 4 APUs, not 8 like we read from other patents.
Moreover they describe 2 chips, the first filled with CPU+DMAC+APUs, the second one composed of CDRAM (Custom Dynamic RAM).
Likely this is just a particular embodiment.
I also noticed that even if in this embodiment thare are 'only' 4 APUs..their respective clocks are skewed by 1/8 of the main 4 GHz clock, not 1/4...does any ring bell there?
Even if you don't want to read the patent, the first figure of the first patent is nice indeed

The third patent can be loosely related to CELL, and it's about fast functions evaluation:

Efficient function interpolation using SIMD vector permute functionality

The last couple of patents (I have still to read them) seem to be about some multiported dram implementation.
That's not my field (like the other patents though ) so maybe someone
like Marco or Simon can help us to understand if they show something new or just basic ideas:

CELL CIRCUIT FOR MULTIPORT MEMORY USING 3-WAY MULTIPLEXER
Cell circuit for multiport memory using decoder

well..that's all folks!

ciao,
Marco

 

[V3]

Again another, great find

I'll read it as I watch the F1 race.

 

[nAo]

Again another, great find

I'll read it as I watch the F1 race.

Unfurtunately I couldn't buy my tickets in time..I live just 150 km away from Imola
Well, I'm gonna watch it in TV!

 

[fxtech]

macchina asincrona ! ta dannnnnn risolto il problema di calore e assorbimento di corrente

sorry i have write in italian

 

[Farid]

They describe how to distribuite power requirements in a PE in space and time. There is a base clock running a 1 GHz, that is multiplied to produce a 2 GHz clock for the DMA Controller and a 4 GHz clock for each APU.

The Ghost of the One TeraFlops machine is haunting another Cell related patent.

 

[Guden Oden]

Not with just 4 APUs per PE though, if there are 4 PEs on the chip...

I am curious, why lock a patent to a particular clock speed anyway? Intel haven't patented every CPU they've ever made at each clock speed it was made available in...

 

[nAo]

Not with just 4 APUs per PE though, if there are 4 PEs on the chip...

One teraflop per second could be reached with 8 PE, 4 APUs per PE.
4 PE on the BE and other 4 PE on the Visualizer

I am curious, why lock a patent to a particular clock speed anyway? Intel haven't patented every CPU they've ever made at each clock speed it was made available in...

I thought the same thing..maybe someone that have experience in this field can give an educated guess..

 

[Farid]

I am curious, why lock a patent to a particular clock speed anyway? Intel haven't patented every CPU they've ever made at each clock speed it was made available in...

Maybe because it's not an "evolutive" piece of hardware, so it clock speed remains the same and could be included in the patent...
But i'm not even sure of this hypothesis because if the actual silicon could not reach (or surpass) the clock speed in the patent , this part of the patent will be kind of useless. :?

Maybe, it's only here as an "example"?

 

[MfA]

Efficient function interpolation using SIMD vector permute functionality

Sounds like a roundabout way of describing SIMD LUT.

 

[Guden Oden]

One teraflop per second could be reached with 8 PE, 4 APUs per PE.
4 PE on the BE and other 4 PE on the Visualizer

Yeah, I guess, provided both chips run their APUs at 4GHz... Oh well, I guess we'll know for sure at next year's E3 at the latest.

 

[David_South#1]

In FIG. 1, two separate electronic chips 100 and 102 are shown separated by a dashed line not designated numerically. The chip 100 includes a plurality of processors, while chip 102 comprises associated memory to be used by the processors of chip 100. As part of the chip 102, there is shown a CDRAM (Custom Dynamic Random Access Memory) 104 and a plurality of combination OCD/OCR (Off Chip Drivers/Off Chip Receivers) operationally two way devices 106, 108, 110, 112 and 114 used for interfacing communication and data transfer between the CDRAM 104 and the CPUs (Central Processor Units) of chip 100.

Paul, are you reading this?

Off chip memory (CDRAM) that sounds something like a XDR 8)
Let me know when the evidence starts proving me wrong.
Becasue right now, it's proving me right.

Also, I predicted out of phase / delayed signaling for the APU last summer and again in December.
http://forum.pcvsconsole.com/viewthread.php?tid=1330&page=6

My only regret is that I didn't revise it with spell check. ;-)

 

[Paul]

Let me know when the evidence starts proving me wrong.
Becasue right now, it's proving me right.

Suzuoki patent is all that matters, you are wrong. Suzuoki's patent is the Toshiba and SCE implementation of "Cell" to craft IC so they can use them in the PS3 as proven by the Rambus, SCE, Toshiba contract. The 64mb of DRAM talked about in the Suzuoki patent is embedded, there is noone that will refute that but yourself.

You argue about crap that everyone has come to a conclusion about months ago and has been proven, Broadband Engine being the core behind PS3, PS3 IC being crafted at 65 nm, e-DRAM on BE, the list goes on.

 

[nAo]

I believe Paul it's right on this point.
This patent talking about 4 GHz APUs and how to better distribuite power, and it takes as problems to resolve power switching on in chip connections and on i/o connections. So they just needed something external to the PE to depict their scenario. (and they don't speak about PE at all..)

 

[David_South#1]

nOa,
Thank you for joining the discussion.
But this patent explicitly says "Fig 1. two separate electronic chips."
That's plain English and very hard to misinterpret or misstate.

Paul,
The newest Suzuoki patent now includes CDRAM <-||-> PE in the drawings.

[0014] The basic processing module is a processor element (PE). A PE preferably comprises a processing unit (PU), a direct memory access controller (DMAC) and a plurality of attached processing units (APUs). In a preferred embodiment, a PE comprises eight APUs.

That is the PE. Then it says

The PU and the APUs interact with a shared dynamic random access memory (DRAM) preferably having a cross-bar architecture. The PU schedules and orchestrates the processing of data and applications by the APUs. The APUs perform this processing in a parallel and independent manner. The DMAC controls accesses by the PU and the APUs to the data and applications stored in the shared DRAM.

"[0065] PE 201 is closely associated with a dynamic random access memory (DRAM) 225 through a high bandwidth memory connection 227. DRAM 225 functions as the main memory for PE 201"

The Patent,
At no time does it say embedded or insinuate that they are packaged together.
Plus they are drawn separately with a high bandwidth connection, not a buss or bit path.
The drawings even illustrate the CDRAM term as linking off chip.
And from the IBM patents, CDRAM is clearly a seperate chip.

CDRAM = XDR,
XDR has a cross bar architecture and can be a shared DRAM.
It is a 64MB chip. And is broken into an 8x8 bank array.

The only eDRAM in an Element,
The VS Visualizer is the only processor with embedded DRAM.
It labels this as “image cache†and states it to be quad-ported.
It also states a storage scheme as 8x 4MB blocks in said Image cache.
They actually state that 4 APU are replaced,
by the presence ‘pixel engine’, ‘image cache’, and CRTc.
If they will draw cache and remove APU for just 32MB,
why wouldn’t they illustrate or mention 64MB to be on chip?

Suzuoki,
If anywhere in the latest Suzuoki patent 20030229765 you find evidence to counter these facts please do share.

Because no matter the odds you say are against me,
this ‘One’ individual has the facts and quotes on his side

 

[nAo]

nOa,
Thank you for joining the discussion.
But this patent explicitly says "Fig 1. two separate electronic chips."
That's plain English and very hard to misinterpret or misstate.

1) My nickname is nAo
2) I can read..in fact if you read my first post in this thread (I found that patent..do you know? ) I wrote the patent talks about 2 chips, one with
APUs, the other one with DRAM.
I'm not saying this is not true, I'm saying that particular patent NEEDS, in order to show its features, an external device. They just used dram, imho.
Moreover there is nothing that prevent to use external dram in CELL architecture.

Paul,
The newest Suzuoki patent now includes CDRAM <-||-> PE in the drawings.

And in Fig.6 it includes a BE and a VS sitting on EDRAM. You can see there is an external memory and a DRAM onto BE and Visualizer chips.

Because no matter the odds you say are against me,
this ‘One’ individual has the facts and quotes on his side.

take your 'facts' better next time.

ciao,
Marco

 

[David_South#1]

nAo,
Sorry about the typo. (How did you come up with that name?)
I also apologize if my greeting was taken wrongly.
So far it’s been Paul for the most part. I like reading other views.
And yes, it was a great find.

As for Figure 6,

In accordance with this modular structure, the number of PEs employed by a member of the network is based upon the processing power required by that member. For example, a server may employ four PEsâ€￾

The wording in this patent hasn’t changed from my sig.
As they have invented a server model they would include a server diagram, yes?

Memory beyond the Mainframe’s Engines?
How many servers don’t have additional DRAM or auxiliary Level 3 caches?

[0059] For example, since servers 108 of system 101 perform more processing of data and applications than clients 106, servers 108 contain more computing modules than clients 106.

Server 108 drawings [fig 6] are needed as server operation and design is discussed.
And a smaller Client 106 [Fig 8 or 9] drawing is also needed as it is discussed.

After all Figure 1. Represents at least 4 examples. Servers use the most Cells.
Wouldn’t you figure that one of the Cell builds would expand on this diagram?

Silent note ~ When was the last time a processor was mounted on eDRAM?
I always thought eDRAM was mounted on it? They enclosed things to tidy the diagram.

I think a lot of you have been ignoring these facts. In your excitement you’ve been choosing the grandest example, forgetting that it needs even grander examples to support it beyond your doorstep.

The world is bigger and brighter than what we know.
David_South, and a few points. You know “simple stuffâ€￾. 8)

 

[nAo]

Memory beyond the Mainframe’s Engines?
How many servers don’t have additional DRAM or auxiliary Level 3 caches?

It's very simple David, a PE doesn't contain any dram, but just SRAM (128k per APU), so that memory HAS to be edram
We don't know if Fig.6 is PS3..but we do know FIg.6 depicts edram.
Moreover standard external dram cannot feed so many APUs without starving some of them

ciao,
Marco

 

[David_South#1]

Very simple? I thought my explanation was to.
But we're still discussing this.

A PE's PU, has registers and memory pools.
A DMAC has registers.
An APU has 2KB registers and 128KB of NORMA SRAM memory.

The Element then has 64MB of XDR or Custom DRAM. ~ Off Chip.

Group 4 PE chips together = Server. FACT FACT !!!
MY god man it says it even time 4 PE are mentioned.

If the BE were an MCM wafer you will place memory on it too.
Fact is that BE doesn't have to be an MCM.
That's a personal guess that fits the depictions.

But it is a fact that the only eDRAM in figure 6 is the Image Caches of the VS group.

Please now, I have shown you that there is no mention of PE eDRAM
That the only time you are led to suspect it is in a Macro view.
And macro views generally obscure finer details.
In all the time that the specific parts are adressed individually.
As BE, PE, VS, etc. The MAIN MEMORY is ALWAYS off Chip.

So please. Give me a fact, a link, a quote something Beyond conjecture.
As of yet I haven't seen better evidence than my own.

Thanks.

BTW- "standard external dram" Who ever said standard? Servers need additional DRAM ~ That's a genral fact. It's also a fact that the patent needs a Server Cell diagram in order to fullfil patent. How come ya'll can't recognize that fact?

 

[Paul]

But it is a fact that the only eDRAM in figure 6 is the Image Caches of the VS group.

And this is quite wrong, The final Broadband Engine may not have e-DRAM, but the 64mb they are talking about in the patent definately IS Embedded.

So please. Give me a fact, a link, a quote something Beyond conjecture.
As of yet I haven't seen better evidence than my own.

How about common sense????

I told you in that other thread;

You don't put external memory on a huge fast bus if you don't have enough memory to store everything needed by the system. It's silly, this is simple stuff David.

What's more, how do you think Broadband Engine would sustain ANYTHING without the e-DRAM? Without it your talking about shit as far as sustained performance, nothing anywhere near a Teraflops. That tiny SRAM won't carry you far.

I think you are just fixated on your current estimations and dont want to back down from them, even when you see such cold fact staring you in the face such as the Rambus, SCE, Toshiba contract which proves that the Broadband Engine is the core IC behind the Playstation 3.

Here is the article that states Toshiba and SCE have liscenced Rambus tech(XDR and Redwood) for PS3;

http://news.com.com/2100-1001-979340.html?tag=fd_top

And here is the contract between the companies

http://library.consusgroup.com/library_pvw/147/147201.asp

Even the date from the article and contract are the same![/i]

 

[David_South#1]

You don't put external memory on a huge fast bus if you don't have enough memory to store everything needed by the system. It's silly, this is simple stuff David.

Now here is a quote from the first link...

Chips churning at that speed, though, need to be surrounded by high-speed links and similarly speedy chips to function properly, which is where Yellowstone and Redwood come in.

This article satifies you speed demands, by saying Yellowstone = XDR.

Now either you consider XDR Embeddeded memory and we have been having a misunderstanding. Or that article backs me up 100% that XDR is the memory solution. Since I consider XDR to be a seperate chip and not embedded. = Me Right, You Wrong???

I don't think you would post evidence that proves you wrong,
so this is my only possible interpretation of the matter.

At no point does it refer to eDRAM that is mounted on the chip.
It says the solution is Yellowstone and Redwood. Both are off chip technologies.

But you still tell me that I am wrong, where is the Proof?
Please show me evidence that proves its on chip.

I don't know, perhaps you've been having some typo problem.
EDRAM means enhanced, eDRAM means embedded. Who knows...
XDR 'is the solution' the article shows and is a seperate chip, so you are wrong.

Right now, I am baffled by how it is that you remain to your statement.