Jawed said:[/list]The leak clearly shows 33.2GB/s from NB-GPU.
Yes, I'm aware as I've stated that before and had people jump down my throat! But the CEDEC diagram above shows only a 'single crossed line' of 22.4 GB/s to the 'memory hub'...
Jawed said:[/list]The leak clearly shows 33.2GB/s from NB-GPU.
Jawed said:So what's that line going through the XPS line buffer then?
Jawed
Jaws said:Well, unless they forgot to put in a cross to suggest it's also bandwidth, to me it's just suggesting 'data flow' to the 'memory hub' shared with the 22.4 GB/s...
Jawed said:Yes, of course
Jawed
Nowhere does the diagram show that. You're confusing "GPU" with "northbridge". The GPU includes northbridge functionality.Shifty Geezer said:Ya know, that above CEDEC diagram is mighty confusing! It shows...
22.4 GB/s Memory controller<> Memory Hub
21.6 GB/s Bus interface<>CPU
16 GB/s Memory Hub > Texture Cache
16 GB/s Memory Hub > Vertex Cache
16 GB/s Resolve and MemExport > Memory Hub
Dependencies/Competing lines don't appear to be shown at all.
Just for confirmation, EVERYTHING to or fro from RAM <> GPU <> CPU consumes part of that GDDR3 22.4 GB/s right? Every CPU code fetch, vertex feed to GPU, direct write from GPU to CPU cache, texture fetch. Any transfer of data is carried on that 22.4 GB/s.
No it doesn't. Look at the DC and IOC on the left.Jaws said:Geez, what's with the rolleys!
Everything that is bandwidth on that diagram has a 'cross'...
This pic, centre-top...Jawed said:Nowhere does the diagram show that. You're confusing "GPU" with "northbridge". The GPU includes northbridge functionality.21.6 GB/s Bus interface<>CPU
It's 10.8 in/out.Shifty Geezer said:Clearly shows CPU only connected to Bus Interface, 10.6 GB/s in, 10.6 GB/s out.
Jawed said:No it doesn't. Look at the DC and IOC on the left.
Jawed
Jawed said:You need to read the lines, not the "touching arrowheads".
Otherwise, you're also left concluding that the 16GB/s of "resolve + shader memory exports" is all going into the Display Controller.
Jawed
I was saying the CPU isn't connected to anything other then BIU, not that the BIU connects to nothing other than CPU. And I'm not really arguing any point about architecture other than the diagram isn't clear. eg. The CPU has 21.4, 21.6 or whatever GB/s to BIU, but unclear data BW from BIU to elsewhere. And it shows 16 GB\s each for textures and vertices which is 32 GB/s, more than the RAM BW. So obviously these are peak figures. But dependencies aren't obvious. eg. Does Vertex data from the CPU eat into the 22.4 GB/s RAM BW, or does it pass through a different line (XPS in the diagram) and thus not eat into the RAM BW?Jawed said:It's 10.8 in/out.
The BIU supports:
Neither x nor y are indicated
- 22.4GB/s bi-directional to the MH
- plus x B/s unidirectional to XPS Line Buffer
- plus y B/s bi-directional to the IOC
Jawed
Jawed said:Well nothing you've pointed out so far supports your argument that 10.8GB/s of procedural data (vertices and textures) from the CPU goes to the GPU along the same data path that data from RAM goes to the GPU, thus hindering the ability of the NB to read from RAM while CPU-GPU data is being transferred.
...
If so, that'll be an effective BW of...Jawed said:I think the XPS Line Buffer is the key. All CPU-GPU data goes via it.
Obviously, all CPU-RAM data has to go via the MC0/1 units, which hinders the ability of the GPU to read/write RAM. That I don't have any argument with. That's the trade-off of a UMA.