New article on Xbox360 GPU

Jawed said:
[/list]The leak clearly shows 33.2GB/s from NB-GPU.


Yes, I'm aware as I've stated that before and had people jump down my throat! But the CEDEC diagram above shows only a 'single crossed line' of 22.4 GB/s to the 'memory hub'...
 
Ya know, that above CEDEC diagram is mighty confusing! It shows...

22.4 GB/s Memory controller<> Memory Hub
21.2 GB/s Bus interface<>CPU
16 GB/s Memory Hub > Texture Cache
16 GB/s Memory Hub > Vertex Cache
16 GB/s Resolve and MemExport > Memory Hub

Dependencies/Competing lines don't appear to be shown at all.

Just for confirmation, EVERYTHING to or fro from RAM <> GPU <> CPU consumes part of that GDDR3 22.4 GB/s right? Every CPU code fetch, vertex feed to GPU, direct write from GPU to CPU cache, texture fetch. Any transfer of data is carried on that 22.4 GB/s.
 
Jawed said:
So what's that line going through the XPS line buffer then?

Jawed

Well, unless they forgot to put in a cross to suggest it's also bandwidth, to me it's just suggesting 'data flow' to the 'memory hub' shared with the 22.4 GB/s...
 
Jaws said:
Well, unless they forgot to put in a cross to suggest it's also bandwidth, to me it's just suggesting 'data flow' to the 'memory hub' shared with the 22.4 GB/s...

Yes, of course :rolleyes:

Jawed
 
Shifty Geezer said:
Ya know, that above CEDEC diagram is mighty confusing! It shows...

22.4 GB/s Memory controller<> Memory Hub
21.6 GB/s Bus interface<>CPU
16 GB/s Memory Hub > Texture Cache
16 GB/s Memory Hub > Vertex Cache
16 GB/s Resolve and MemExport > Memory Hub

Dependencies/Competing lines don't appear to be shown at all.

Just for confirmation, EVERYTHING to or fro from RAM <> GPU <> CPU consumes part of that GDDR3 22.4 GB/s right? Every CPU code fetch, vertex feed to GPU, direct write from GPU to CPU cache, texture fetch. Any transfer of data is carried on that 22.4 GB/s.
Nowhere does the diagram show that. You're confusing "GPU" with "northbridge". The GPU includes northbridge functionality.

XPS is Xbox Procedural Synthesis. That would be all the vertex and texture data from CPU to GPU, at a guess.

Obviously the GPU can also read vertex and texture data from RAM, separately.

Jawed
 
Jawed said:
21.6 GB/s Bus interface<>CPU
Nowhere does the diagram show that. You're confusing "GPU" with "northbridge". The GPU includes northbridge functionality.
This pic, centre-top...
012l.jpg


Clearly shows CPU only connected to Bus Interface, 10.6 GB/s in, 10.6 GB/s out.
 
Am i the only one to have noticed the BIG sign saying "Microsoft Confidential" at the bottom of that picture?
Not that i really care, but it's not very confidential now is it...:devilish:
 
Shifty Geezer said:
Clearly shows CPU only connected to Bus Interface, 10.6 GB/s in, 10.6 GB/s out.
It's 10.8 in/out.

The BIU supports:
  • 22.4GB/s bi-directional to the MH
  • plus x B/s unidirectional to XPS Line Buffer
  • plus y B/s bi-directional to the IOC
Neither x nor y are indicated

Jawed
 
Jawed said:
No it doesn't. Look at the DC and IOC on the left.

Jawed

Now when I look at the memory hub, any arrows 'touching' it shows direction of data flow to/from the memory hub. In fact there are arrows all over the diagram that are not stating bandwidth but data flow. Only arrows with 'crosses' are showing bandwidths...and only 22.4 GB/s is shown as aggregate to the 'memory hub'...now that diagram may not be consistent/ erroneos/ not clear...but that is what it's showing...
 
You need to read the lines, not the "touching arrowheads".

Otherwise, you're also left concluding that the 16GB/s of "resolve + shader memory exports" is all going into the Display Controller.

Jawed
 
Jawed said:
You need to read the lines, not the "touching arrowheads".

Otherwise, you're also left concluding that the 16GB/s of "resolve + shader memory exports" is all going into the Display Controller.

Jawed

That' not concluded at all...that b/w simply goes to the 'memory hub'...
 
Well nothing you've pointed out so far supports your argument that 10.8GB/s of procedural data (vertices and textures) from the CPU goes to the GPU along the same data path that data from RAM goes to the GPU, thus hindering the ability of the NB to read from RAM while CPU-GPU data is being transferred.

I think the XPS Line Buffer is the key. All CPU-GPU data goes via it.

Obviously, all CPU-RAM data has to go via the MC0/1 units, which hinders the ability of the GPU to read/write RAM. That I don't have any argument with. That's the trade-off of a UMA.

Jawed
 
Jawed said:
It's 10.8 in/out.

The BIU supports:
  • 22.4GB/s bi-directional to the MH
  • plus x B/s unidirectional to XPS Line Buffer
  • plus y B/s bi-directional to the IOC
Neither x nor y are indicated

Jawed
I was saying the CPU isn't connected to anything other then BIU, not that the BIU connects to nothing other than CPU. And I'm not really arguing any point about architecture other than the diagram isn't clear. eg. The CPU has 21.4, 21.6 or whatever GB/s to BIU, but unclear data BW from BIU to elsewhere. And it shows 16 GB\s each for textures and vertices which is 32 GB/s, more than the RAM BW. So obviously these are peak figures. But dependencies aren't obvious. eg. Does Vertex data from the CPU eat into the 22.4 GB/s RAM BW, or does it pass through a different line (XPS in the diagram) and thus not eat into the RAM BW?
 
Am I the only person who, whenever I come across a technical discussion between Jaws and Jawed (and there are a few), imagines a schizophrenic hunched over their keyboard, holding a bizarre conversation amongst themselves in two completely different accents?

Maybe it's just me...
 
Jawed said:
Well nothing you've pointed out so far supports your argument that 10.8GB/s of procedural data (vertices and textures) from the CPU goes to the GPU along the same data path that data from RAM goes to the GPU, thus hindering the ability of the NB to read from RAM while CPU-GPU data is being transferred.
...

Errm...I've just stated on several occasions that there are no 'crossed' arrows that represent bandwidth to the memory controller that's greater than 22.4 GB/s and I've also stated the 'text' from the 'xenon leak' from last year. I'm not pulling this out of thin air...
 
Jawed said:
I think the XPS Line Buffer is the key. All CPU-GPU data goes via it.

Obviously, all CPU-RAM data has to go via the MC0/1 units, which hinders the ability of the GPU to read/write RAM. That I don't have any argument with. That's the trade-off of a UMA.
If so, that'll be an effective BW of...

10.6 RAM to CPU (code and data)
22.4-10.6 = 11.8 RAM to GPU (texture, vertex etc.)
10.6 CPU to GPU via XPS (procedural data)

for 33.4 GB/s, or something like that. But if XB360 has this direct data feed to GPU without going thtough RAM, why haven't MS said something of the sort? We know PS3 has a dedicated CPU<>GPU data flow, and MS have been quick to identify other data bandwidths they have such as eDRAM data. Why not this dedicated line that effectively frees up 10 GB/s if really present?
 
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