Nehalem Desktop Roadmap Leaked
- Thread starter ShaidarHaran
- Start date
Westmere, and the 32nm process, is a (late) 2H '09 product.
Which is probably what AMD's Bulldozer is going to be facing.
I think a 4C/8T Nehalem will be a good upgrade from my E6300
I think you're right.
I'm sitting on an E8400 that can hit 4GHz with relative ease (albeit rather high volts) so I think I'll wait out Nehalem. I'd like to hold off until Sandy Bridge, but if the 32nm process brings significant clockspeed scaling improvements to the Nehalem family (i.e. Westmere) then I may go that route.
Specious1600
Newcomer
Hmm, Nehalem looks great. It's too bad I can't and won't be able to afford it at launch. Ah well, it's not like my Q6600 is going to feel "slow" anytime soon. Or is it? Ah, such is the face of the rapidly evolving technological world!
Sorry if this has been discussed already but could someone walk me through why aren't the northbridge and southbridge merging into a single chipset now that the memory controller in integrated into the CPU?
I would think that just leaving the northbridge with, essencially, babysitting the graphics PCIe slot is a terrible inefficiency but perhaps there are other, non-technical issues at stake like wields and whatnot.
I would think that just leaving the northbridge with, essencially, babysitting the graphics PCIe slot is a terrible inefficiency but perhaps there are other, non-technical issues at stake like wields and whatnot.
The remaining chipset functionality is dirt-cheap to manufacture. There's no real cost savings or performance benefit to be had from integrating these onto the CPU die at this point. Also, motherboard manufacturers wouldn't be too happy about the matter, as it would make product differentiation even that much more difficult in an already over-crowded market.
No, no. I'm not talking of integrating the remaining chipset functions into the CPU, only merging the northbridge and southbridges into a single chipset now that the northbridge is twiddling its proverbial thumbs.
Pardon the misunderstanding. NV must not yet be capable of hosting all the requsite PCI-e 2.0/1.x lanes on a single chip, yet. Probably easier to physically route traces for two chips in different directions/areas of the board in some respect as well.
Blazkowicz
Legend
well look at this http://en.wikipedia.org/wiki/Nehalem_(microarchitecture)#Variants
cheaper and mobile variants of nehalem are said to include a dual channel memory controller, PCIe 2.0 and DMI (a bus that goes to the southbridge).
number of PCIe lanes is unspecified.
cheaper and mobile variants of nehalem are said to include a dual channel memory controller, PCIe 2.0 and DMI (a bus that goes to the southbridge).
number of PCIe lanes is unspecified.
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