See the GF4 capacitors in action (one pic):
http://www.nvmax.com/cgi-bin/nvmax.pl?action=news&num=1015042352
Matrox codename Parhelia again and Matrox G450 x4 MMS PCB de
- Thread starter Nappe1
- Start date
Nebuchadnezzar
Legend
This is nice:
A guy posted an Article about the Parhelia
http://www.matroxusers.com
And that in two months!
A guy posted an Article about the Parhelia
http://www.matroxusers.com
And that in two months!
On 2002-03-07 18:59, Nebuchadnezzar wrote:
This is nice:
A guy posted an Article about the Parhelia
http://www.matroxusers.com
And that in two months!
"3. It is fast. It will have a new memory design, different from all current video cards. Memory speed will be faster than the current fastest (a GeForce4). Faster by a huge margin of victory."
eDRAM? - say 2Mb maybe for the Z buffer.
I think VigilAnt knows very well what he is talking about, I think he said things the way he did because he didn't want to reveal too much detail. Well, we'll just have to see, right?
As for the people on the forums, we are currently a little out of our minds because of joy. You would be too if you had waited three years for another high end part :rollseyes:
Not all of us are geniuses of course, and not all know their 3D terminology inside out. But we know what we like, and we have been brought together by our love for the quality of Matrox hardware :smile:
BTW. I agree that http://www.mu.com/ is a waste of space.
Joe DeFuria
Legend
Well, the the different ways marketers "claim" bandwidth depth, it wouldn't surprise me much at all if it was actually 128 or 256 bit.
It might be a 256 bit wide DDR interface, and the inference is that "it's effectively a 512 bit interface, therefore not 128 or 256."
Who knows.
It might be a 256 bit wide DDR interface, and the inference is that "it's effectively a 512 bit interface, therefore not 128 or 256."
Who knows.
I my calculations are right (or close!) 400Mhz memory with a 192-bit interface would yield bandwidth of around 18Gbps (19.2 if you do the old Gigabyte "equals" 1000000000 bytes calculation).
This would tie in with the bandwidth figures floating around. I've seen several people who have a bit of knowledge say that a 192-bit interface might be viable.
If the chip does, indeed, exist and is 192-bit, it will be interesting to see what form of Occlusion culling it might do also.
This would tie in with the bandwidth figures floating around. I've seen several people who have a bit of knowledge say that a 192-bit interface might be viable.
If the chip does, indeed, exist and is 192-bit, it will be interesting to see what form of Occlusion culling it might do also.
Joe De Furia: well in that MURC news thingy they are talking about chip bus. Not memory bus. So, if you have 256Bit DDR memory interface, would that mean that your chip must have 512Bit data bus inside, because with 256Bits inside the chip isn't enough for handling all data coming from that memory bus.
am I right? :smile: if yes, then that easily explains it being 512Bit chip. :smile:
I'm certain it has been done in lots of hardware. The P4 has a DDR ALU for instance, but I'd think it's more common for DDR tech to be used for buses of various kinds. AGP2x is a DDR btw, AGP4x is QDR. If I'm not mistaken I think ethernet in fullduplex mode is some sort of DDR too (like read on falling edge, write on rising).
Companies might use an internal DDR bus and not release that information, because it doesn't affect the function of the chip so developers don't need to know it. One thing I've heard that might make DDR buses less useful for internal wiring is that it is more difficult to use a DDR bus when the bus isn't point to point.
well yes, but it was a Dual Channel 128Bit, was it? so if I am not mistaken, it couldn't handle 128Bit DDR memory, because both channels could not be operated same direction at the same time. IN/IN or OUT/OUT wasn't possible, but it was very powerful for 128Bit SDR memories because it was capable doing IN/OUT or OUT/IN. (Both Channels worked separately. so while data from/to memories was using first channel, 2nd channel could have been used for chip's internal transfers.)
I am an loysy explainer as you can see, but hopefully someone got the idea. :smile:
Using both rising and falling edges of a clock cycle is used in more than just RAM. AGP, the P4's FSB, the Athlon's FSB, Caches for various MPUs and the list goes on, basically wherever one cannot implement a faster or wider bus, double pump it.
As for the G400 has dual internal 128 bit buses that do NOT extend outside of the chip in anyway, they are used to access the on chip frame buffer tile cache or texture cache (can't remember) so that it could be read from and written to in the same clock. And before anyone goes nuts, the G400 isn't a deffered tile render, it simply tiled the frame buffer.
Nappe1, it kinda sounds like you're implying that these busses extended outside the chip, when they are purely internal. I think they did something simillar with the G200, except with dual 64bit buses.
As for the G400 has dual internal 128 bit buses that do NOT extend outside of the chip in anyway, they are used to access the on chip frame buffer tile cache or texture cache (can't remember) so that it could be read from and written to in the same clock. And before anyone goes nuts, the G400 isn't a deffered tile render, it simply tiled the frame buffer.
Nappe1, it kinda sounds like you're implying that these busses extended outside the chip, when they are purely internal. I think they did something simillar with the G200, except with dual 64bit buses.
Ascended Saiyan
Newcomer
I don`t think that would be possible if this chip is already in its alpha stage.I could be wrong though because Matrox is also known for introducing exotic memory types & it might be possible.ronaldo said: