hahahahaha
Something is not right. Each CELL APU burns only 1 watt @ 0.9 V at 2 Ghz???? 11 watts at 5 Ghz??? If IBM had such technology, it can forget about making chips for a living, license that tech to Intel and make billions/year.
I will wait for the full set of slides posted to analyze CELL. Because this smells very fishy indeed.
http://www.electronicsweekly.co.uk/articles/article.asp?
liArticleID=38754&liArticleTypeID=1&liCategoryID=1&liChannelID=114&liFlavourID=1&sSearch=&nPage=1
"
The busses connect to the SPEs through local memory, 256kbyte for each SPE. The developers have tested the memories to 5.4GHz at 1.3V and 52°C."
4-5+ Ghz was the SRAM speed and not the ALU speed.
Now it makes perfect sense, CELL ALUs run at 1/4th the clock of XDR input signal. In other world, that 4 Ghz input = 1 Ghz internal operating clock.
This is funny as hell. The whole processor industry used upcloking(internal clock is X times higher than input clock) since 486, SCEI is the first to use downclocking in recent history.
In other word, 4 Ghz XDR clock = 1 Ghz CELL ALU operating clock.
Now it makes perfect sense, CELL ALUs run at 1/4th the clock of XDR input signal. In other world, that 4 Ghz input = 1 Ghz internal operating clock.
I have seen no evidence that suggests that CELL really runs at 5 Ghz. In fact, SCEI's refusal to claim 256 GFLOPS in press release would suggest it does not. Kutaragi Ken is the kind of person who would do such a shameless thing if it was possible on paper, but even he does not do it.
All the transistor and thermal information on CPU core of CELL suggests it is indeed a sub 1.4 Ghz design. You will have to wait until the slides are posted at Japanese sites sometime tomorrow to make it official. IBM's own CPUs fail to clock past 2.5 Ghz, so why should I believe that a 5 Ghz processor exists???
But note: "The Rambus XDR memory interface, capable of data rates of 3.2GHz to 8.0GHz." The question is how much bandwidth will the PS3 CELL memory have.
