ISSCC 2005

[McFly]

The FlexIO technology will be used to connect the various chips on a Cell-based motherboard, according to Rich Warmke, marketing director of the memory interface division at Rambus. A multicore Cell processor, by contrast, will use its own internal bus to connect multiple cores. However, 90 percent of the Cell's external pins are connected to either the FlexIO or XDR interfaces, evidence that the Cell's design emphasizes moving application and or 3D scene data around within main memory, Warmke said.

http://www.extremetech.com/article2/0,1558,1761407,00.asp

So a multi PE chip is planned at least.

Fredi

 

[j^aws]

So, not a sniff of any eDRAM for CELL

 

[PiNkY]

Intel released additional details on its Montecito chip. 1.72 Billion transistors at 90 nm. Small scale availability is 4Q05

 

[Squeak]

So, not a sniff of any eDRAM for CELL

You mean 256Kb for each SPU and 100Gb/s of low latency main mem bandwidth isn't enough?!

 

[McFly]

Intel released additional details on its Montecito chip. 1.72 Billion transistors at 90 nm. Small scale availability is 4Q05

A one PE cell has 234M transistors, so a 6 PE chip is more than possible.

Fredi

 

[nAo]

IIRC each bit in a sram does cost 6 transistors + 1-2 transistors. Let's assume a bit costs 7 transistors.
Let's also assume the main CPU core has a 512 kb L2 cache and 32 kb L1 cache.
Then total amount of sram on chip should be 256*8+512+32 = 2592kb (!!)
How many transistors does this sram cost?
2592*7*2^13 = 150 MTransistors, and this is just for cache and local memory!
So about 84 Mtransistors are left to be used in chip logic.

ciao,
Marco

EDIT: I have never seen a so long ''Users browsing this forum' bar, LOL

 

[j^aws]

So, not a sniff of any eDRAM for CELL

You mean 256Kb for each SPU and 100Gb/s of low latency main mem bandwidth isn't enough?!

Yes! ...j/k

I thought I'd raise the point because there was alot of talk on that subject from the original CELL patents early on...it seems they've gone for a nice cache hierarchy from recent patents...

 

[V3]

So about 84 Mtransistors are left to be used in chip logic.

Between the 9 cores, DMA and controller, that's not alot of logic.

 

[V3]

A one PE cell has 234M transistors, so a 6 PE chip is more than possible.

If Kutaragi has really taken over Sony, perhaps, we'll see it in PS3. If not we will see something like that in IBM server instead.

 

[Paul]

A multicore Cell processor, by contrast, will use its own internal bus to connect multiple cores.

The Broadband Engine.

 

[Titanio]

A one PE cell has 234M transistors, so a 6 PE chip is more than possible.

If Kutaragi has really taken over Sony, perhaps, we'll see it in PS3. If not we will see something like that in IBM server instead.

I think he's kidding

1 PE looks pretty solid to me now. 2 at the very most (but quite unlikely, I think).

 

[McFly]

A one PE cell has 234M transistors, so a 6 PE chip is more than possible.

If Kutaragi has really taken over Sony, perhaps, we'll see it in PS3. If not we will see something like that in IBM server instead.

I think he's kidding

1 PE looks pretty solid to me now. 2 at the very most (but quite unlikely, I think).

I think we are both kidding. I personaly expect 2PE and hope for 4 PE. 8)

Fredi

 

[j^aws]

Anyone worked out if Moore's law has been beaten!?

 

[archie4oz]

What's to work out? Moore's law is all about density/transistor count... So no, it hasn't been beaten...

 

[Acert93]

http://rambus.com/news/newsroom/pressrelease.cfm?id=162

Good stuff there:

The memory and processor bus interfaces designed by Rambus account for 90% of the Cell processor signal pins, providing an unprecedented aggregate processor I/O bandwidth of approximately 100 gigabytes-per-second.

100GB/s? Wow. Now we can hope for 512MB But note: "The Rambus XDR memory interface, capable of data rates of 3.2GHz to 8.0GHz." The question is how much bandwidth will the PS3 CELL memory have.

PS3 is really shaping up to be a performance monster.

 

[V3]

With 100 GB/s I/O, they can just put 4 (65nm or 90nm) Cell chips and call it Broadband Engine, if they wanted too.

 

[j^aws]

What's to work out? Moore's law is all about density/transistor count... So no, it hasn't been beaten...

I was referring to the relative performance figures for CELL given those parameters.

 

[mistan]

So whats going on?!
umm, did the conference take place yet?
has the paper reached the internet?
can somebody plz announce it whenever its scanned to the internet
so 256g/flops is concrete then?
any benchmarks?
real world performance numbers?

 

[nAo]

Good article with nice pics :
http://www.electronicsweekly.co.uk/...14&liFlavourID=1&sSearch=&nPage=1

From the pics it's easy to see PPE L2 cache size is 512 kb.
SPUs also have a big chunk of logic devoted to double precision processing..
I think that would be very appreciated for all that folks that do physics/scientific calculations

ciao,
Marco

 

[ChryZ]

It became 24 in the last 10 min

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now its 70, every freekin site is reporting about it