ISSCC 2005
- Thread starter ChryZ
- Start date
Ok...that does make sense, I'm overspeculating.MfA said:I think the estimate is simply the lookup, if so you still have to do the Newton-Rhapson iteration ... which is going to take 1 or 2 multiply accumulates.nAo said:So can we say the shortest vertex trasformation loop is just 5 cycles?
Now please, someone find me the ultimate SPE ISA Book
*waiting for the "WHAT? 6GPolys is only 90 times more than PS2's peak!!! They said 1000times better!! EVIL SONY!" comments*
ISSCC 2005: The CELL Microprocessor, by David T. Wang @ Real World Technologies
Panajev2001a
Veteran
MfA said:I think the estimate is simply the lookup, if so you still have to do the Newton-Rhapson iteration ... which is going to take 1 or 2 multiply accumulates.nAo said:So can we say the shortest vertex trasformation loop is just 5 cycles?
Yes, but the same value can be re-used: Vertex Position, Color and ST Texture Coordinates. So the effective latency for the "division" is a bit lowered.
sonycowboy
Newcomer
one said:
In this article, the writer states the following:
"The obvious advantage of the XDR memory system is the bandwidth that it provides to the CELL processor. The less obvious drawback is that it is a memory system designed specifically for a high performance embedded system. Particularly, the maximum of 4 DRAM devices means that the CELL processor is limited to 256 MB of memory, given that the highest capacity XDR DRAM device is currently 512 Mbits. While the capacity of limit of 256 MB or even 512 MB of memory would not limit the expected primary application of the CELL processor, the capacity constraint does present itself as an issue in applications where large memory capacity is needed alongside high DP FP throughput and high bandwidth. Clearly, the CELL processor is currently not suitable for these environments, but the high speed FlexIO may enable the use of an external memory controller where multiple channels of high frequency, Fully Buffered Dimms may be attached to retain the bandwidth capability but solve the capacity constraint issue. Incidentally, Toshiba is a manufacturer of XDR DRAM devices. Presumably it brought the XDR memory controller and memory system design expertise to the table, and could ramp up production of XDR DRAM devices as needed."
This seems to state that currently, the CELL is limited to 256MB XDR DRAM. How does this affect the capability of the PS3 having 512MB (or more) and what impact will it have on the CELL's usage in other areas. Basically, is this a problem?
sonycowboy
Newcomer
Titanio said:
If there are multiple PE's does that mean that they will have non-unified memory space? I seem to recall that that was a very positive aspect of the Xbox design that the 64MB was accessible from anywhere.
sonycowboy said:
Cell has 3 (or 2 dependend on how define it) Interfaces:
1 XDR Interface which is limited to 4 64Bit Modules (the one currently limited to 256MB)
1 coherent FlexIO
1 noncoherent FlexIO
Ive taken those details from http://www.realworldtech.com/page.cfm?ArticleID=RWT021005084318 and dont fully understand the difference between coherent and noncoherent, but the article hints that only the noncoherent Part of the FlexIO Interface will be used for the PS3.
My interpretion is that the coherent Part would allow memory-sharing between Cells / other Parts (GPU?) while making sure the caches dont interfere ( Memory is coherent between Cells ).
I supposse the PS3 could sport something like the Amiga`s Fast- and Chip-Ram. FastRam( the 256MB on the XDR IF) being used primary by the Cell and ChipRam beeing used by the GPU and eventual other Chips.
Possible Config 1 (PS3 & 512MB NUMA ):
256 MB "FastRam" for Cell
256 MB "ChipRam" for the GPU, effectively the GPU would have the same Memory-Interfaces as Cell (FlexIO for Connection to Cell, XDR for RAM).
I would like to see a PE beeing integrated in the GPU aswell, but thats just me
Possible Config 2 (aimed at Desktops):
256 MB "FastRam" for Cell, noncoherent FlexIO connected to GPU/Northbridge. coherent FlexIO connected to more casual DDRRam-Controller (Chipram).
london-boy said:Jaws said:Thanks to M.Isobe at Ars, sorry if old...
Wow, they got it up to 5.2GHz. Wonder how long the chip lasted at that speed...
I'm surprised no one has noticed this yet...
@ 5.0 GHz, SPE is 63 degC
@ 5.2 GHz, SPE is 61 degC
Conclusion: CELL starts COOLING past 5.2 GHz and is best served CHILLED! 8)
Aw... I was hoping you'd just be able to crack it up to 10ghz and have NO thermal output!
sonycowboy said:
I think you get more info at the other thread
UMA sucks and splits the bandwidth and it's definitely a bad thing for Cell, btw.Question from the Ascii24 article,
"The instruction length of SPE at 32bit fixed length, becomes the instruction format, 3 source registers and 1 target register."
There are 128 registers ergo 28bits are needed to specify four registers, leaving 4bits for instructions. This doesn't seem like much - presumably a lot of instructions don't use four registers and so can use the extra bits but it still seems....odd. Anyone have any clues onto how the instruction set will work?
Oh and if the GPU isn't connected to the EIB on the PS3 I will be surprised.
"The instruction length of SPE at 32bit fixed length, becomes the instruction format, 3 source registers and 1 target register."
There are 128 registers ergo 28bits are needed to specify four registers, leaving 4bits for instructions. This doesn't seem like much - presumably a lot of instructions don't use four registers and so can use the extra bits but it still seems....odd. Anyone have any clues onto how the instruction set will work?
Oh and if the GPU isn't connected to the EIB on the PS3 I will be surprised.
Well there is another level to the speculation - how often can the lookup be issued in the first place?(we only "know" the throughput for MADDs so farnAo said:
) If I can issue one every cycle that'd be a major boon not to mention It'd mean smallest transform would be limited solely by MADDs in that case.Similar threads
