High-performance one-transistor memory cell
Abstract
One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.
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[0008] The above mentioned problems are addressed and will be understood by reading and studying this specification. This application discusses improved memory cells fabricated without integrated capacitors. These memory cells provide DRAM-like density, faster SRAM-like performance, and improved scalability. Various aspects of the present invention relate to high-density and high-performance memory devices that bridge the application requirements for DRAM and SRAM. The memory cells include a single transistor having a floating node and an integrated diode with an intrinsic region (e.g. p/i/n or n/i/p diode). The intrinsic region of the diode holds the memory state, and thus can be used to replace complex capacitor fabrication of the conventional DRAM device. Various embodiments are implemented in bulk silicon technology, and various embodiments are implemented in semiconductor-on-insulator or silicon-on-insulator (SOI) technology. Various embodiments gate the integrated diode to enhance speed and reduce standby power for the memory cell. Gate-controlled integrated diodes are particularly useful for the bulk implementations. SOI implementations use floating body charges to enhance operation and performance such that, in various embodiments, the SOI memory cell includes a diode without gate control. Various embodiments include laterally-oriented diodes, and various embodiments include vertically-oriented diodes.
[0009] One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. The intrinsic region holds the potential of the floating node and thereby the memory state of the memory cell. Other aspects and embodiments are provided herein.
