Intel has a tiler?

[Dave B(TotalVR)]

http://www.intel.com/design/graphics2/zr.htm

Zone Rendering 2 Technology is a unique technology developed by Intel for drawing (rendering) 3D graphics scenes. This technology optimizes system memory usage by reducing the required memory bandwidth for the graphics engine.

The 3D graphics engine divides the frame buffer into rectangular zones and then sorts the triangles into memory by zone. The 3D graphics engine then completely processes the zone, writing the pixel data to memory before proceeding to the next zone. By processing only a single zone of the frame buffer at a time, the use of on-chip memory (cache) is highly optimized and each pixel in each scene is drawn only once. As a result, the system memory bandwidth required to render each scene is greatly reduced. This ensures the most efficient system memory usage for optimal graphics and system memory performance.

Zone Rendering 2 Technology increases performance over the original Zone Rendering Technology by enhancing architectural efficiencies in both hardware and software.

This isn't powervr mbx is it!?!?

 

[Dave Baumann]

Good god, this dates back years IIRC. 865 was a Tiler.

[Edit] Clicks on the link, and sure enough it references 865. No, this isn't MBX.

 

[arjan de lumens]

Intel integrated graphics solutions have had tile-based rendering for ages, and these are not based on PowerVR technology. Unlike the PowerVR solutions, they don't appear to have any kind of efficient overdraw removal, so performance and efficiency are generally not very good. IIRC, you can even run the Intel solutions in immediate mode too if you need to; this gives even worse performance.

 

[Carl B]

Yeah Intel IGP solutions have been tile-based for quite some time now. Their architecture deviates from PowerVR's implementations, but it's interesting to note that Intel does hold a license for MBX.

 

[Ailuros]

Tile based definitely yes, deferred I'd rather say debatable (from the few debates about it from the past).

 

[Ailuros]

..... but it's interesting to note that Intel does hold a license for MBX.

And Eurasia/SGX obviously.

 

[Fox5]

Tile based definitely yes, deferred I'd rather say debatable (from the few debates about it from the past).

Hasn't every video card since the geforce 3 been tile based?

 

[Simon F]

Hasn't every video card since the geforce 3 been tile based?

Is that "tile" with a little 't' or a capital 'T'?

What you are probably thinking of is the arrangement of framebuffer memory in rectangles rather than scanlines and the rendering of the trianges pixels in that order. This reduces memory pagebreaks.

 

[mczak]

IIRC, you can even run the Intel solutions in immediate mode too if you need to; this gives even worse performance.

Indeed, the dri driver (xfree86/xorg) does not support zone rendering. Setup would be more complicated, afaik you need to send geometry data more than once.

 

[Dave B(TotalVR)]

Tile based definitely yes, deferred I'd rather say debatable (from the few debates about it from the past).

actually, now I remember something about that a while ago. hopefully we might see sgx integrated into intel chipsets soonish....

would be interesting with an sgx AIB, the scalability is likely very flexible indeed, could you 'sli' an sgx AIB with an integrated chip? so long as you have a data path between the two i dont see why you couldn't.

 

[Ailuros]

I'm a layman but it sounds extremely dumb to me to scale chips for an integrated sollution when you can in fact scale units. Smallest PDA/mobile SGX according to IMG's claims takes up 2 mm^2, while the largest sollution goes to 8 mm^2. I can't possibly decypher yet what each contains but I could dare to guess that in the latter they might scale Z/stencil and ALUs amongst others to increase performance.

Scale that up by Nx times until you reach a reasonable die space for an IGP and I don't see why they'd need to scale chips here.

 

[Ailuros]

Is that "tile" with a little 't' or a capital 'T'?

What you are probably thinking of is the arrangement of framebuffer memory in rectangles rather than scanlines and the rendering of the trianges pixels in that order. This reduces memory pagebreaks.

Voodoo1 alert

 

[deviantchild]

http://www.intel.com/design/graphics2/zr.htm



This isn't powervr mbx is it!?!?

That'll teach you for scraping about at the bottom of the bin for PowerVR news, Dave! LOL - Take a day off, on me.