Intel cancels plans for highest-speed Pentium 4 chip

[Accord1999]

Cache isn't cheap at all, that's completely wrong.
He's confusing the design complexity related costs - which are already paid: your engineer are FT not extra personnel - with manufacturing cost.

It's completely true. Cache is cheap relative to logic, especially given Intel's unmatched manufacturing capabilities. An extra 1MB of cache will add 20-25mm^2 to the die size of Prescott, maybe an extra $5 in manufacturing costs at most.

 

[Fox5]

Cache isn't cheap at all, that's completely wrong.
He's confusing the design complexity related costs - which are already paid: your engineer are FT not extra personnel - with manufacturing cost.

It's completely true. Cache is cheap relative to logic, especially given Intel's unmatched manufacturing capabilities. An extra 1MB of cache will add 20-25mm^2 to the die size of Prescott, maybe an extra $5 in manufacturing costs at most.

And $5 is what? Like 25% of the cost of the chip?

 

[Accord1999]

It could be, but that's not as important as the average selling price, which for Intel is over $150. If the extra cache can increase the average selling price by more than $5 than its a win.

 

[T2k]

Cache isn't cheap at all, that's completely wrong.
He's confusing the design complexity related costs - which are already paid: your engineer are FT not extra personnel - with manufacturing cost.

It's completely true. Cache is cheap relative to logic, especially given Intel's unmatched manufacturing capabilities. An extra 1MB of cache will add 20-25mm^2 to the die size of Prescott, maybe an extra $5 in manufacturing costs at most.

Let me rephrase: cache isn't cheap relative to logic because it adds more than a half of the die size, bigger than rest of the chip. (Although definitely cheaper than having external cache, of course.)
If it wouldn't be true, why Intel didn't add MORE cache to compete?

 

[OICAspork]

I agree for the P4 EEs that cache is being thrown in to combat the on-die memory controller. Though technically they aren't throwing cache onto a desktop P4, just rebranding a Xeon.

For Dothan, I'm not so sure. At the time of its design I don't think it was meant to compete directly with a desktop A64 or FX. The successor to Dothan might be more informative.

Then why don't Intel work towards incorporating a memmory controller into their CPUs? I haven't heard of any work in this direction (not that this is something I follow that closely)... but wouldn't that in and of itself very likely flip the power struggle well into Intel's favor? I know that isn't something they can just toss out there, but given a couple of years (and they've already had about a years notice of the advantages AMD is getting from this), couldn't this be incorporated into their architecture?

 

[3dilettante]

I agree for the P4 EEs that cache is being thrown in to combat the on-die memory controller. Though technically they aren't throwing cache onto a desktop P4, just rebranding a Xeon.

For Dothan, I'm not so sure. At the time of its design I don't think it was meant to compete directly with a desktop A64 or FX. The successor to Dothan might be more informative.

Then why don't Intel work towards incorporating a memmory controller into their CPUs? I haven't heard of any work in this direction (not that this is something I follow that closely)... but wouldn't that in and of itself very likely flip the power struggle well into Intel's favor? I know that isn't something they can just toss out there, but given a couple of years (and they've already had about a years notice of the advantages AMD is getting from this), couldn't this be incorporated into their architecture?

I believe there is a bit of speculation (but no hard evidence that I know of) that Intel is working towards integrating a memory controller.

However, it looks like it might not be until FB-DIMMs are out. The interface is markedly lower in pin count compared to the DDR interface being used by AMD, and in theory it should help keep a processor from being so tightly tied and limited to a single memory technology.

 

[Killer-Kris]

I agree for the P4 EEs that cache is being thrown in to combat the on-die memory controller. Though technically they aren't throwing cache onto a desktop P4, just rebranding a Xeon.

For Dothan, I'm not so sure. At the time of its design I don't think it was meant to compete directly with a desktop A64 or FX. The successor to Dothan might be more informative.

Then why don't Intel work towards incorporating a memmory controller into their CPUs? I haven't heard of any work in this direction (not that this is something I follow that closely)... but wouldn't that in and of itself very likely flip the power struggle well into Intel's favor? I know that isn't something they can just toss out there, but given a couple of years (and they've already had about a years notice of the advantages AMD is getting from this), couldn't this be incorporated into their architecture?

I believe there is a bit of speculation (but no hard evidence that I know of) that Intel is working towards integrating a memory controller.

However, it looks like it might not be until FB-DIMMs are out. The interface is markedly lower in pin count compared to the DDR interface being used by AMD, and in theory it should help keep a processor from being so tightly tied and limited to a single memory technology.

Actually a couple little birdies have told me a few different things.

- The main reason that Intel hasn't already done an on chip MC is that the suites are afraid of the memory standard changing. Remember rambus? They'd hate to be stuck in an even worse position.

- From the time of Timna, there have been several pet projects where the MC was on chip. All of which unfortunately have been canceled.

- Tejas derivatives where to be the first P4s with ondie MCs, those of course were all canceled.

- Cedarmill and other Prescott derivatives may/maynot (It's been claimed that they won't need it, so what ever that means ) have ondie MCs.

 

[Killer-Kris]

Cache isn't cheap at all, that's completely wrong.
He's confusing the design complexity related costs - which are already paid: your engineer are FT not extra personnel - with manufacturing cost.

It's completely true. Cache is cheap relative to logic, especially given Intel's unmatched manufacturing capabilities. An extra 1MB of cache will add 20-25mm^2 to the die size of Prescott, maybe an extra $5 in manufacturing costs at most.

Let me rephrase: cache isn't cheap relative to logic because it adds more than a half of the die size, bigger than rest of the chip. (Although definitely cheaper than having external cache, of course.)
If it wouldn't be true, why Intel didn't add MORE cache to compete?

So according to your line of reasoning, x87, MMX, SSE, 3DNow, etc... all should have never been added to the chips because they cost transistors and increased die size? Not only is cache more dense than logic (ie. lower cost), it also tends to help in a larger range of cases than most logic that gets added with the exception of an ondie MC.

And while Intel has chosen to add enough cache that it ends up being more than 1/2 the total die, cache by default doesn't add up to more than 1/2. That is just what Intel chose because of variables we likely have no knowledge of, yield, partially defective cores, performance increase per engineer hour (somewhere cache is very much cheaper than logic), verification time, and many others. They could have chosen to add a smaller ratio, 1/10, 1/4, 1/3, or a larger one 9/10 but they didn't because it wasn't ideal for their particular microarchitecture.

 

[T2k]

Cache isn't cheap at all, that's completely wrong.
He's confusing the design complexity related costs - which are already paid: your engineer are FT not extra personnel - with manufacturing cost.

It's completely true. Cache is cheap relative to logic, especially given Intel's unmatched manufacturing capabilities. An extra 1MB of cache will add 20-25mm^2 to the die size of Prescott, maybe an extra $5 in manufacturing costs at most.

Let me rephrase: cache isn't cheap relative to logic because it adds more than a half of the die size, bigger than rest of the chip. (Although definitely cheaper than having external cache, of course.)
If it wouldn't be true, why Intel didn't add MORE cache to compete?

So according to your line of reasoning, x87, MMX, SSE, 3DNow, etc... all should have never been added to the chips because they cost transistors and increased die size? Not only is cache more dense than logic (ie. lower cost), it also tends to help in a larger range of cases than most logic that gets added with the exception of an ondie MC.

How did you get there? I'm curious...

All I'm saying it isn't exactly true that cache is cheap. It isn't true at all.
Manufacturing, wafer - everything means cost for the chip maker.
Just think about this: if they haven't had cache at all, Intel would have made 2x more chip from the same wafer.
I exaggerate this, sure but only for the sake of understanding.
Everything comes down to money, believe me.

And while Intel has chosen to add enough cache that it ends up being more than 1/2 the total die, cache by default doesn't add up to more than 1/2. That is just what Intel chose because of variables we likely have no knowledge of, yield, partially defective cores, performance increase per engineer hour (somewhere cache is very much cheaper than logic), verification time, and many others. They could have chosen to add a smaller ratio, 1/10, 1/4, 1/3, or a larger one 9/10 but they didn't because it wasn't ideal for their particular microarchitecture.

That's pure speculation, you have nothing to back up.
I mean for example currently less than 2MB cache is not enough, means nothing but wasted space in terms of competing with AMD.
They had to come up with something against AMD's integrated controller - and less than 2MB is useless, we can see from the benchies.
Moreover ANY chip's cache is at LEAST 1/3rd big - so this whole speculation is false, I think.

 

[3dilettante]

- The main reason that Intel hasn't already done an on chip MC is that the suites are afraid of the memory standard changing. Remember rambus? They'd hate to be stuck in an even worse position.

In theory, the FB-DIMM standard Intel is pushing so hard should remedy this. Basically, memory technologies of all types can interface through a specialized buffer chip on the DIMM, and so would appear to the CPU to be using the same signaling protocol. In theory, one could have a DDR DIMM translated through a buffer alongside a DDR2 or XDR DIMM using its own buffer. The timings might need to be very conservative, but it could be workable.

However, the buffer and serial bus add a bit of latency, so it wouldn't easily match the low latency offered by a specialized memory controller on die. On the other hand, FB-DIMM would really help with a lot of the signal skew and crosstalk problems that parallel memory buses suffer from.

We might finally be able to have more than 2 DIMMs per channel at DDR400 speeds (or was that 1 DIMM per channel at DDR400). It's probably not a big factor for desktops, but servers would love that.

 

[Saem]

As things head more and more towards multimedia and people are very interested and will be further enabled to setup HTPC, thanks to PCI express, a very fast memory sub system would be well come. Mind you bandwidth is more important than latency in this case, but reducing latency can increase bandwidth given the right situation.

 

[Killer-Kris]

Cache isn't cheap at all, that's completely wrong.
He's confusing the design complexity related costs - which are already paid: your engineer are FT not extra personnel - with manufacturing cost.

It's completely true. Cache is cheap relative to logic, especially given Intel's unmatched manufacturing capabilities. An extra 1MB of cache will add 20-25mm^2 to the die size of Prescott, maybe an extra $5 in manufacturing costs at most.

Let me rephrase: cache isn't cheap relative to logic because it adds more than a half of the die size, bigger than rest of the chip. (Although definitely cheaper than having external cache, of course.)
If it wouldn't be true, why Intel didn't add MORE cache to compete?

So according to your line of reasoning, x87, MMX, SSE, 3DNow, etc... all should have never been added to the chips because they cost transistors and increased die size? Not only is cache more dense than logic (ie. lower cost), it also tends to help in a larger range of cases than most logic that gets added with the exception of an ondie MC.

How did you get there? I'm curious...

I'll admit, I was making a huge stretch but that doesn't completely invalidate it. You are saying that Intel shouldn't be adding cache because it's expensive and takes up die space, well all these other features do as well, should they have not been added? I think we'll all agree that they should have been, just like more cache is always better.

All I'm saying it isn't exactly true that cache is cheap. It isn't true at all.
Manufacturing, wafer - everything means cost for the chip maker.
Just think about this: if they haven't had cache at all, Intel would have made 2x more chip from the same wafer.
I exaggerate this, sure but only for the sake of understanding.
Everything comes down to money, believe me.

I agree it definitely does come down to money, and I think that's precisely why Intel has been using such large caches. There is an ideal die size, and if you can't make use of it with logic given the time constraints, you add what features you can, and then fill the rest of your space with cache.

You might notice that both Dothan and Banias are almost the exact same size? I wonder if there is something in particular about that size, perhaps the best price/size ratio and if Dothan just didn't come close to filling that space they'd certainly be better off filling that extra space with cache. That and using cache likely uses significantly less power than pulling data out of memory and over the bus. So it's actually something quite pertinant to the design of Dothan as part a whole system.

That's pure speculation, you have nothing to back up.
I mean for example currently less than 2MB cache is not enough, means nothing but wasted space in terms of competing with AMD.
They had to come up with something against AMD's integrated controller - and less than 2MB is useless, we can see from the benchies.
Moreover ANY chip's cache is at LEAST 1/3rd big - so this whole speculation is false, I think.

Well I'm curious if you're talking about the 2MB Prescotts or Dothan versus A64, because from the few benchmarks I've seen Dothan in most cases is slightly faster (clock for clock) in integer and branching benchmarks, and A64 is slightly faster in floating point and memory dependant benchmarks. Over all they're pretty darn close, and with the extra pipeline stages a desktop Dothan with the gloves off would have a much better time scaling in clock speed versus an A64, than Coppermine did against Thunderbird.

Now of course if you're talking Prescott :-/ well I definitely agree they need an ondie memory controller badly. And the adding the extra cache is almost certainly a matter of attempting to gain performance where as with Dothan it certainly seemed to be for a whole different reason.