Okay, they will maybe write a wrapper. Guess it will be much slower than DLSS on nVidia hardware so developer will use it like DLSS as a libary with interfaces. Do not think anybody will rewrite it for TensorCores.
Intel ARC GPUs, Xe Architecture for dGPUs [2018-2022]
- Thread starter DavidGraham
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Okay, they will maybe write a wrapper. Guess it will be much slower than DLSS on nVidia hardware so developer will use it like DLSS as a libary with interfaces. Do not think anybody will rewrite it for TensorCores.
Also with their Raytracing Units (one thing without a fancy name, what a delight!) - they do traversal as well.
DegustatoR
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I've been saying for some time now that Nv should've ported DLSS to something widely compatible too.
Would've likely lead to low resolution slideshows on cards without ML h/w in the same fashion as RT did on Pascals.
...And everyone would be happy...
DegustatoR
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Intel Xe-HPC Ponte Vecchio GPU features up to 128 Xe-Cores and 128 Ray Tracing Units
Less SIMDs per MP but twice wider?
One would say that such config would be a better fit for gaming.
Less SIMDs per MP but twice wider?
One would say that such config would be a better fit for gaming.
D
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At the timestamp, they say they "will open up the tools and SDKs" of XeSS for everyone.
Could we see XeSS on consoles?
Could we see XeSS on consoles?
Bondrewd
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Yes.
They run packed math like every other RDNA2 part out there.
DegustatoR
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I kinda wonder what backend a console would run a SYCL code through? Is there anything in modern console APIs which is compatible with SYCL compilers?
Bondrewd
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The slideware says it's very much fast enough
D
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So is Intel going to sell their their own graphics cards and use their CPU distribution channels?
Intel's video mentions ISVs "and partners", but I heard no mention of any AIBs specifically.
That could be one way to avoid GPU hoarding at the manufacturing plants' exit.
Intel's video mentions ISVs "and partners", but I heard no mention of any AIBs specifically.
That could be one way to avoid GPU hoarding at the manufacturing plants' exit.
DegustatoR
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Come to think of it, Nv doesn't have an SYCL backend either, do they?
Where are the ms figures on that "slideware"?
You sure it's simply RPM? I've not checked out any of this yet.
One thing that is nice is that my interpretation of something they said months ago turned out to be right.
So I'm not surprised they have ML upscaling and plan to open source it, as it was exactly as I expected.
Depending on price they could have some very compelling products, even if its at the mid to lower end of performance
Bondrewd
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Codeplay is writing one.
The same place as native 4k FPS number there.
Yes. Makes sense. So why has Intel Matrix engines when DP4a is "very much fast enough"? Even on the illustration slide it takes at least twice as long.
DegustatoR
Legend
So nowhere. This slide means little and is basically an artistic drawing of intent. We have to wait for the actual code to say anything on how it will perform on different h/w.
Codeplay is targeting OpenCL which is basically Z-class citizen on Nv h/w.
And CUDA choices are down to Intel and AMD implementations right now I think?
Bondrewd
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Selling ML into the wider market.
What actually ships in millions of units aka iGPs has none of XMX bs.
And they need Matrix engines for it when they can use just DP4a?
Turing delivers 4x more INT8 performance with TensorCores than with DP4a. And you saying that 1/4 INT8 performance is "very much fast enough" for ML approaches?
/edit: Looked at DLSS and it scales just fine with more compute performance:
3090 vs 2060 Super: 2,5x more FP16 performance with TensorCores is 2,5x faster with DLSS Performance scaling a 1080p -> 2160 picture.
Turing delivers 4x more INT8 performance with TensorCores than with DP4a. And you saying that 1/4 INT8 performance is "very much fast enough" for ML approaches?
/edit: Looked at DLSS and it scales just fine with more compute performance:
3090 vs 2060 Super: 2,5x more FP16 performance with TensorCores is 2,5x faster with DLSS Performance scaling a 1080p -> 2160 picture.
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