Inductive Coupling

I am assuming that the cost of dram die will go up in proportion to the number of TSVs required.
Only with laser drilling (and I doubt it makes a huge difference there). EVG uses etching to create the holes for TSVs ... at which point all the steps to create them are process steps for which the number doesn't matter.

Presumably the die size of the DRAM would be ~50 mm2 or so, so you could either put one or multiple stacks beneath the GPU to vary the memory bus size on large GPUs.
 
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If it is indeed an acceptable way, I wonder why most introductory materials I come across suggest putting the logic die (cpu or gpu) underneath arguing it has more bonds.

There has to be some tradeoff in putting the DRAM below which I am missing.

My guess is that DRAM underneath won't work out until both the IHV's can agree on this.
 
It avoids the hassle of having to connect the remaining solder bumps under the top die to the bottom substrate, if you look at the patent Jawed linked the process is quite involved, a lot of the research is aimed at increased integration for low power mobile chips ... not increased bandwidth for 100 W/cm2 chips. Top mounting makes sense for the former, bottom for the latter (at least IMO, I think for top mounting microfluidic cooling or embedded heatpipes are pretty much a necessity).

PS. Jawed didn't mention this, but I assume it's how he found it in the first place ... AMD is not the assignee on that patent, but a couple of those inventors were also inventors on a double concentric ring via patent application for ATI ... the plot thickens ;) (Inventors don't have to register an assignee, so the patent is likely still owned by AMD ... unless these guys went freelance to patent troll).
 
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