IBM Power 7 @ HotChips
- Thread starter ShaidarHaran
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It looks like the TDP isn't completely out of the question, however I understand its a very complicated issue. Its just great to know that theres another viable processor architecture our there for me to speculate about.
I believe Power6 had some limited out-of-order stuff, it was for the floating point unit and according to their tech doc: "In general, the POWER6 processor is an in-order machine, but the BFU instructions can execute slightly out of order.... At most, eight FPU instructions can be issued out of order from the FPQ."
So it sounds like even the float unit didn't have the its ooo capability to the same degree as the older Power CPUs. So I'm just wondering if they really brought it back to the same level they had before.
So it sounds like even the float unit didn't have the its ooo capability to the same degree as the older Power CPUs. So I'm just wondering if they really brought it back to the same level they had before.
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An interesting note about the EDRAM density from Hans de Vries @ Ace's:
Would be more interested in Nehalem EX's L3 density than any IPF chip, given the older/larger process node(s) always involved in that sort of comparison.
Would be more interested in Nehalem EX's L3 density than any IPF chip, given the older/larger process node(s) always involved in that sort of comparison.
...and latency. The EX L3-Cache architecture seems to be the same as the power7 architecture with 3 MB associated with each Core. Link: http://www.semiaccurate.com/2009/08/25/intel-details-becton-8-cores-and-all/
Hans de Vries said 5.7mm²/MB for standard Nehalem, http://aceshardware.freeforums.org/finally-an-image-of-shanghai-t405-15.html, presumably EX will be similar? Would be nearly factor 3 in size difference, but without knowing latency that doesn't mean much (though over at aceshardware they seem to think the ibm edram latency is quite low).
As a side note, as usual intel got way higher cache density than AMD (comparable density for L2 but intel is using 8T-sram for that...).
I did some searches about the differences between DRAM and SRAM, I also want to learn more about Edram (forgive my ignorance 
) thus I spent some time on wiki. I find a link to this article (I know it's pretty old but it's the only thing I found).
here a quote:
) thus I spent some time on wiki. I find a link to this article (I know it's pretty old but it's the only thing I found).here a quote:
May be it can help you.
I saw Paul's comments in that same thread but didn't want to quote them because of his disclaimer at the end.
So no one outside IBM knows the real latency figure for Power 7's L3 as of yet. Will be interesting to revisit this thread once we do know, though.
So no one outside IBM knows the real latency figure for Power 7's L3 as of yet. Will be interesting to revisit this thread once we do know, though.
It's possible, but right now we don't know how this fares in a consumer oriented application compared to, say, a Bloomfield, which is roughly 260mm2 with 4 cores.
Why 3-Core?
Why not a "simple" 1/2 POWER7 4-core CPU with 16MB eDRAM and ~280mm² @ 4GHz with ~ 65-70Watt (based on pcchens estimate of 130-140 Watt for the Power7 CPU). Could be cometitive with other 4 core CPUs but with the energy consumption of some 2 core CPUs.
Quoting myself
According to this link: http://forums.amd.com/devblog/blogpost.cfm?catid=271&threadid=103010
the AMD Shanghai CPU has a L3-Latency of 29 cycles.
So the Power7 eDRAM L3-Cache could be faster than the SRAM Cache of the AMD Shanghai. If that is true than the eDRAM L3-Cache would IMHO really be a breakthrough.
From what I've heard, the maximum die size Microsoft would accept is 180 mm2.
OK, somehow I overlooked the reference to the XBox3 CPU in your first posting.
Not saying down-sized power7 would make sense or not, but surely by the time xbox3 would appear it would use at least cpu manufactured in 32nm, hence it would fit nicely.
If you measure the POWER7 die shot, each core, with its associated L2 cache, is only about 30 mm^2. That's about the same size as one core of the current Xbox 360 CPU. A console-destined POWER7 variant could be even smaller because there would be no need for the full four double-precision floating point units. (One should be enough for a console application.) I strongly suspect that IBM will use the POWER7 as the basis for the PPE' (<-- note the "prime") in the PowerXCell 32ii and 32iv.
