http://pc.watch.impress.co.jp/docs/2003/1027/kaigai038.htm
Babelfish reckons :-
"The delay reason of Prescott finally clarification
- With bus interface trouble stepping modification
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- Prescott of the mPGA478 edition where meaning becomes thin
Big Æ’gÆ’Q which sticks to the throat of Intel, that is the next generation CPU of Intel "Prescott (the press cot)". The shipment of Prescott approximately 1 quarter in lag and present schedule, ships to the OEM vendor into year, latter half from the of January of the next year has become announcement between the February head. That, after the shipping whether how much quantity is supplied there is a circumstance which is not visible.
First existing chip set and the existing motherboard (in case of Prescott FMB1.5 conformity) you can use Prescott of the mPGA478 edition which is thrown, that way. But, also meaning of existence of this mPGA edition Prescott, steadily is thinned by lag. Because in other words, new LGA775 socket edition Prescott+Grantsdale (Æ’Oƒ‰ƒ“ƒcÆ’fÂ[ƒ‹) chip set + it changes to new motherboard specifications Prescott FMB2 2004 2nd quarter.
As a result, mPGA478 edition Prescott+Prescott FMB1.5 approximately 1 only quarter is becoming something which is not meaning. After that mPGA478 edition Prescott and as for the Socket478 platform •¹ sale it is done with say, as for charm it is scanty. If when, the quantity of shipment of mPGA478 edition Prescott during next year 1st quarter will be small with this, meaning of existence of mPGA478 edition probably will be gone almost.
When it becomes so, the positioning of Prescott is difficult to Intel. As for Intel 0.13 ƒÊ m edition Pentium 4 (Northwood: It is the intention the north wood) of stopping in 3.2GHz and to the cartridge, throwing Prescott from 3.4GHz. But, when only the quantity where the 3.4GHz is limited it stops being able to put out, it is not good. On the other hand, making the release of Prescott LGA775 edition time be delayed, the to high clock converting Northwood to 3.4GHz, perhaps between that it does the selection that, it makes relay.
In any case, the lag of Prescott has produced big effect around.
- Problem occurs in bus interface
The cause Prescott being late for a long time was unclear. But, as for Intel presently, concerning the cause Prescott being late, vis-a-vis the customer you say that is information is made clear.
First, as for fundamental problem, when mPGA478 edition Prescott of present B step is loaded onto the motherboard of existing Intel 865/875 chip set, you say that the case where bus error occurs has been found. In other words, it is the case that what can test Prescott of present condition and the place, with the motherboard of expectation of Prescott ready, cannot guarantee operation is ascertained. You say that because as for the cause of that, voltage amplitude of bus interface came out, the case which is not agreeable to the specifications which are stipulated. By the way, in LGA775 edition this problem it is not, (or it solves on motherboard side? ).
System bus of Pentium 4/Prescott type AGTL+ (Assisted Gunning Transceiver Logic) uses signal technology. With AGTL+ of Intel, focusing on reference voltage "GTLREF", acquiring the small amplitude of the Â}10% to voltage, it transmits. Referring to GTLREF, it decides receiver side, whether the signal high the low/row. By the fact that voltage amplitude is designated relatively as single breadth, high-speed transmission is made possible. GTLREF is supplied, being formed on motherboard side.
As for the latest problem, those where with combination of mPGA478 edition Prescott and 865/875 motherboards, voltage of the high level time occurred, the value which it is stipulated with AGTL+ (VIH) with the case which does not coincide. As for VIH minimum GTLREF+10% and maximum Vcc, as for VIL maximum GTLREF-10% and minimum has become with 0. But, Prescott of present condition with combination of 865/875, the case which on high side is not settled in the framework of VIH occurred, it seems. As for Intel you say that when error occurs due to the operation of system bus, it was found.
This problem is solved, which of CPU side or motherboard side must be modified. However, chip set and the motherboard have already appeared in the market with Prescott ready, modification is difficult after so long a time. Because of that, Intel has made the correction of Prescott unavoidable. Intel has notified the fact that it copes with approach of 2 stages vis-a-vis this problem to the customer, it seems.
- Modifying the package and silicon at 2 stages
As for 1st step method, as for Prescott itself with while it is existing B0 step, the method of solving with the package.
Concretely, it disconnects GTLREF from the motherboard, however, forming GTLREF inside the package, it supplies to CPU. It is the case that by the fact that GTLREF which this anew is formed is shifted from established value, you supply signal input inside the range of VIH. If this, it is possible to place existing Prescott B step, in the existing 865/875 motherboards. In the tip/chip and both of the motherboards modification means there is no necessity.
However, unless correspondence can do with this method to only FSB 533MHz, you call Intel that it has explained. Because Prescott of the Pentium 4 brand is the schedule of FSB 800MHz, to that it means not to be able to use. In other words, Prescott which modifies just the package is the case, Prescott exclusive use of the Celeron system of FSB 533MHz.
Then, Intel 2nd with step, has been about to modify also the circuit design of Prescott in addition to package modification.
Intel presently the sample as for Prescott which is being shipped B0 step. This B0 step was offered to each vendor at the time of September COMPUTEX,, but none of them was operational 2.8GHz (FSB 800MHz) to at only low frequency. Perhaps this, the fact that the latest problem occurs remarkably with the tip/chip of higher clock operation than 2.8GHz is meant. Intel increasing this to C step, has been about probably to assure the solution of problem.
With C step, as for Intel you say that the circuit design of input sense amplifier of the system bus of Prescott was modified. Prescott is operated with FSB 800MHz, you say that combination of this C step and the revised edition mPGA package is necessary. Intel is advancing the company internal verification of C0 step at October point in time, says that it is the schedule which ships the sample of C1 to December vis-a-vis each vendor.
- The mass production of schedule harsh Prescott
If you look at this plan, lag of mPGA478 edition Prescott is rather heavy. Because revision change of silicon is needed, FSB 800MHz edition Prescott completely 1 means quarter to be delayed.
Intel is the plan that it starts the mass production with C1 step to end of year, but Qualification Sapmle (QS) with directly mass production considerably tight is schedule in December. Usually, Bali day Shaun ending, letting flow the wafer to Fab, until it reaches the point where it can ship the tip/chip of the finished product abundant, there is a time lag of 2 - 3 months. Because of that, whether the Prescott tip/chip of how much quantity comes out at point in time of next year 1st quarter it is unclear. From the circumstance such as that, spring of next year it is the model in industry, and others there is a voice which is worried about the supply of Prescott.
In addition, as for this method of forming GTLREF inside the package, a rather with Æ’gÆ’Å Æ’bÆ’LÂ[, certain industry authorized personnel is surprised "to there ugly (is scurvy) solution expedient is taken, cannot believe Intel," that.
You do not know source fundamental of the latest problem is somewhere. Perhaps, perhaps the electric power consumption = supply electric flow of Prescott rising from the simulation of beginning, is related with this problem.
In addition, this problem has shown also the difficulty which supports two CPU generations with the same motherboard. If Intel had modified with Prescott every chip set/the motherboard, CPU side was not modified and perhaps also the ‚Ä was completed. Actually, with LGA775 edition Prescott+Grantsdale chip set, it seems that is not such problem.
- Modifying just the package, it throws as Celeron?
In addition, as for being another doubt Intel prepares also the solution of the B0 step + revised edition package. If just C0 step should have been shipped gently, the sea urchin it is visible. Why, as for Intel the revised edition of B0 step you probably will prepare specially.
One what can be presumed, is the possibility Intel already having held Prescott of B0 step in large quantities. In order to relieve the stock of the B0 tip/chip of the dying body, perhaps Intel of such solution expedient was thought.
Actually, also modification of this place of the product plan of Intel corresponds. Intel around summer of this year changed the plan of Prescott forward fall had decided to throw Prescott of the Celeron brand for the value market suddenly, next year 2nd quarter. Usually, after new architecture of Intel & CPU of new process appearing in for the high end, it gets off to 4 about quarter it is required for the value market. However, with Prescott, only 1 quarter and Celeron class appears at speed of exceptional case.
The for the sake of there isa room to which "column with Intel of the time before the Prescott strategy acceleration, price edition throwing,as for this yield rate of the 90nm process of Intel is good next year 2nd quarter low," takes the bold strategy it had presumed. But, in order to relieve Prescott of the B0 step which, already is really produced perhaps is. In other words, with FSB 800MHz perhaps it puts out with FSB 533MHz the tip/chip which cannot be put out, as Celeron.
- To Prescott FMB2 Intel which is shifted
In any case, because of substantial lag, mPGA478 edition Prescott is diluting existence value. LGA775 package edition Prescott of one side, when it is satisfactory, calls Intel that you say. Simply, LGA775 because it is not supported with only Grantsdale chip set, becomes the completion waiting of Grantsdale and ICH6. Grantsdale is the place where presently finally the sample is being supplied.
Though, rather perhaps the real start-up of Prescott for Intel, the one which slips in the combination with Grantsdale is more convenient. In other words, by the fact that the specifications of the motherboard are changed to Prescott FMB2, at a stroke TDP (Thermal Design Power: Because thermal design electric power consumption) and it is possible to pull up the specifications of supply electric flow. Actually, as for Intel as for mPGA edition Prescott with end, you call above 3.8GHz with 3.6GHz that it supplies in only LGA775 edition, it seems. If you say opposite, Prescott above 3.8GHz that much is the case, troublesome tip/chip which consumes many electric power.
Assuming, that and, the motherboard specifications were pulled up even if with Prescott FMB2, it does not solve problem with that. In other words, as for the motherboard design to become more difficult with Icc increase, because with the rise of TDP the thermal design of PC itself becomes difficult. As for a certain industry authorized personnel "so far as for PC steadily the basket body was made small, but with Prescott the flow changes. It cannot avoid "becoming large, that you say.
The limit of the strategy of Intel in the various aspects is visible in Prescott.
