How would one go about confirming the exact position of unused circuitry on a modern chip?

Discussion in 'Architecture and Products' started by Randomoneh, Mar 20, 2021.

  1. Randomoneh

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    Let's say a large hardware benchmarking group had a hypothesis that disabled circuitry on a cut down version of the chip (for example 3060Ti, cut from full GA104, 2070 Super cut from TU104 or any cut down modern CPU) is positioned always in the exact same spot and not randomized throughout the surface, as would be expected if cut-down chips were salvaged from semi-failed chips.

    How could anyone confirm that? NO2 + thermal imaging? Something simpler?
     
  2. Davros

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    Id say thermal imaging
    not sure if it would work but maybe also an mri machine (moving electrons generate a magnetic field)
     
  3. Qesa

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    Being able to see the die without it immediately overheating is gonna be the problem. Maybe immersion cooling and thermal imaging?
     
  4. Randomoneh

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    Serious downvolting and downclocking combined with very cold closed space like a fish tank or styrofoam box with NO2 and a pointed fan inside the box to dissipate heat might work.

    What do you guys think, what would we observe if we could see this - randomly positioned dead area or always the same place.

    Seeing how most of the cost for producing modern chips comes from R&D and fabs and marginal cost (cost of each new unit) of chips themselves is relatively low, I'd expect chips that fail to be discarded completely and not salvaged in any way and cut down chips to be made by disabling full chips.
     
  5. arandomguy

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    Do you mean that there is no "legitimate" binning at all? There's obviously "working" chips that are artificially disabled to ensure supply to various configurations but there is a "legitimate" binning due to actual yield loss as well. There's been occasions manufacturers have been more specific in terms of what they bin. Also for some single configuration products there is cut portions to alleviate yield issues (notably the consoles), if yield loss were actually trivial that would not be done.

    Physical defect yield loss is not the only consideration. Parametric yield loss is less talked about it seems but is there as well.
     
  6. Jensen Krage

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    There are two videos that come to mind showing tours of NVIDIA's Failure Lab. They go through some of the machines and processes that NVIDIA uses to see how their chips perform. Probably a decent place to start if trying to figure out what parts of chips are not used; however, the machines are pretty expensive.

    One is from Gamer's Nexus on YouTube called "NVidia Silicon Failure Analysis Lab Tour - How It's Made" (2013)

    Another is from Blunty on YouTube called "Nvidia FAILUREā€¦ Lab - AMAZING Behind The Scenes Tour" (2016)
     
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  7. Rys

    Rys Graphics @ AMD
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    In a design where you can disable one or more processing blocks and keep a working chip, you always* build in the ability to selectively disable the right block instance. When that's done at testing time, for yield reasons, these days it's usually disabled via a blown e-fuse.

    *you don't have to, but it'd be mad not to. Defects are random on the wafer surface, so only giving yourself the same physical block(s) to disable would significantly hurt your chance of harvesting a working chip when faced with a defect.
     
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  8. 3dcgi

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    There is definitely salvaging of chips that are broken.
     
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  9. Naitsabes

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    If the circuits were really cut and not just disabled by software: OBIRCH and/or EMMI
     
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