Hmm...this coupled to MBX Pro might work well.

[Lazy8s]

The average overdraw typical to a Naomi 2 game would be higher than that of a Naomi game since development for Naomi 2 has been more recent and because it would be doing higher polygon densities.

 

[Lazy8s]

Speaking of Naomi 2, these look like new screenshots for Virtua Fighter 4: Final Tuned -

 

[London Geezer]

Nice, but Lazy, will you ever post screens that are bigger than 30x20??

 

[Fox5]

Speaking of Naomi 2, these look like new screenshots for Virtua Fighter 4: Final Tuned -

Texture and environment wise it still looks like a dreamcast game, though those two characters look like they have 3x the amount of polys. I think sega should upgrade to triforce or chihiro, or throw in an extra naomi. This game may look better in some areas than current systems could do, but it lacks in others.

 

[PC-Engine]

Dude have you actually seen any videos of VF4 on NAOMI 2? Better yet have you seen the actual arcade units? They look nothing like those screenshots. Those tiny screens look horrible!

 

[Sonic]

I'm very close to purchasing a VF4 Evo arcade cabinet. Sad thing is I won't be getting it from within the company as there are none available. But the man who is selling it is a reseller and has very expensive prices, don't really know whether it is worth it or not.

I think MBX Pro and this ARM chip would make for a lethal combination and would be perfect for MS to get into the hand-held market with.

 

[Jabjabs]

From what I've heard over the years this is how I see the DC PVR chip.

It may of only run at 100 megapixels but due to the deferred/tile based rendering none of it was wasted on over draw, only alpha blanding and transparency. This meant that when counting transparency, the maximun overdraw you could have is 2-3x, but other wise it is only limited to the limitations of the PVR deferred rendering capabilities of which I heard was upto 60x overdraw.

I'm noy 100% sure about these figures but I'm sure some of it is correct.

 

[Fafalada]

This meant that when counting transparency, the maximun overdraw you could have is 2-3x, but other wise it is only limited to the limitations of the PVR deferred rendering capabilities of which I heard was upto 60x overdraw.

I heard something like the pixels reject rate of 40/clock (should really ask Simon to verify this if he can though) which could give you a bit higher overdraw then 60x.
Speaking of this, interesting note is that modern rasterizers have early Z test that rejects at like 256pixels/clock - so the overdraw elimination is even "more free" nowadays even though we don't use tilers

 

[Megadrive1988]

From what I've heard over the years this is how I see the DC PVR chip.

It may of only run at 100 megapixels but due to the deferred/tile based rendering none of it was wasted on over draw, only alpha blanding and transparency. This meant that when counting transparency, the maximun overdraw you could have is 2-3x, but other wise it is only limited to the limitations of the PVR deferred rendering capabilities of which I heard was upto 60x overdraw.

I'm noy 100% sure about these figures but I'm sure some of it is correct.

I'm sure most if not all of what you said here is correct. this is pretty much exactly what I've read about the PowerVR2DC / CLX chip.

 

[Lazy8s]

The CLX's maximum sort depth is 60 - it's fillrate can effectively range between a high of 3.2 Gpixels/sec when there's total overdraw (scenes of just opaque polygons) and a low of 100 Mpixels/sec when there's no overdraw to take advantage of (scenes of only transparent polygons).

 

[Simon F]

This meant that when counting transparency, the maximun overdraw you could have is 2-3x, but other wise it is only limited to the limitations of the PVR deferred rendering capabilities of which I heard was upto 60x overdraw.

I heard something like the pixels reject rate of 40/clock (should really ask Simon to verify this if he can though)

32 per clock.

Speaking of this, interesting note is that modern rasterizers have early Z test that rejects at like 256pixels/clock

That's not what I've heard quoted and the performance benchmarks don't indicate it either. I believe it might be more like 16~32 per clock on the early Z reject.

 

[Simon F]

The CLX's maximum sort depth is 60 .

What? You can put as many polygons in (with different depth) as you like (memory permitting on CLX). There is no opaque "depth sort" limit because depth comparsions are done with an internal Z-Buffer.

There may or may not (it's too long ago for me to remember) be a limit to how many intersecting layers of translucent polygons it will per-pixel-sort, but you'll hit a practicle performance limit, due to fill rate, first.

 

[Lazy8s]

Simon F:

What? You can put as many polygons in (with different depth) as you like (memory permitting on CLX). There is no opaque "depth sort" limit because depth comparsions are done with an internal Z-Buffer.

There may or may not (it's too long ago for me to remember) be a limit to how many intersecting layers of translucent polygons it will per-pixel-sort, but you'll hit a practicle performance limit, due to fill rate, first.

Right, that's what would make sense, and I'd think that areas of 60x overdraw would give an effective fillrate of 6 Gpixels/sec too. It was this listing which confused:

The system ASIC combines a PowerVR rendering core with a system bus controller, implemented using a 0.25-micron, five-layer-metal process. Imagination Technologies (formerly VideoLogic) provided the core logical design and Sega supplied the system bus. NEC provided the ASIC design technologies and chip layout, including qualification for 100-MHz operation. Fill rates are a maximum of 3.2 Gpixels per second for scenes comprising purely opaque polygons, falling to 100 million pixels per second when transparent polygons are used at the maximum hardware sort depth of 60.

http://www.computer.org/micro/articles/dreamcast_2.htm

 

[Teasy]

Speaking of this, interesting note is that modern rasterizers have early Z test that rejects at like 256pixels/clock - so the overdraw elimination is even "more free" nowadays even though we don't use tilers

Well it would be insanly pointless to have 256pixel per clock rejection in 2000 when Kyro was released wouldn't it

Also with the high inefficiency of early pixel rejection on current IMR the actual pixel rejection is far from the theoretical 256 pixels. My Radeon 9700 Pro can't get close to its peak fillrate (2.6Gpixel/s) with 20GB/s memory bandwidth. Where as my old Kyro 2 can hit 100% of its 350mpixel/s fillrate with just 2.7GB/s bandwidth. Actually I noticed the other day that the Radeon 9700 and the Kyro II have pretty similar Villagemark scores

 

[Fafalada]

That's not what I've heard quoted and the performance benchmarks don't indicate it either. I believe it might be more like 16~32 per clock on the early Z reject.

Well I should have been more specific, the number was referring to X800, and it's theoretical max for hierarchical Z reject, so granted it's not always gonna reject at that speed
Thanks for the correct numbers for DC btw.

Actually I noticed the other day that the Radeon 9700 and the Kyro II have pretty similar Villagemark scores

Well as noted I was thinking X800. And anyway, on these chips you'd want to render something like a Z-only pass first to get optimal overdraw elimination.

 

[SegaR&D]

The GPU in the Hikaru was indeed designed in-house.