G73 has 4 Quads/16 pipelines?

[DSC]

http://www.digit-life.com/articles2/video/g71-part2.html

Using the new beta of RivaTuner we found out that G73 contains four quads instead of three (16 pipelines)! One quad is just disabled (locked on the hardware level and cannot be unlocked). It all means that in future we may see something like 7600 GTX with 16 pixel pipelines, as the process technology is streamlined. In that case there will rise a question whether the memory bandwidth is sufficient for this core (the bus is 128-bit). But first of all, it's just an assumption, such GPU may be never launched; secondly, as memory prices go down, these cards may be equipped with the fastest memory, which will make up for the narrow bus; thirdly, there appear new games, which require GPU performance in the first place, not memory bandwidth; fourthly, there is some chance that designers made a mistake in registers and that's why the program detects an extra quad, which does not exist (that's not likely, but to err is human).

Interesting. I wonder whether it really has 4 quads or not.

 

[MuFu]

Hard to imagine that's the case. Not only because the die is tiny, but because I have great faith in the Waveys of this world to sniff out such things prior to launch.

 

[Geo]

Hrmph! And if G73 is "1/2 a G71"? :smile:

My head is starting to hurt again.

 

[Bob]

G73 has 3 quad pipes (12 fragment pipes). Sorry to disappoint.

 

[Geo]

G73 has 3 quad pipes (12 fragment pipes). Sorry to disappoint.

Looking forward to Unwinder's explanation then!

 

[Xmas]

fourthly, there is some chance that designers made a mistake in registers and that's why the program detects an extra quad, which does not exist (that's not likely, but to err is human)

And of course, the most likely possibility is that RivaTuner is making a mistake in wrongly interpreting register values as a quad "locked on the hardware level and cannot be unlocked"...

 

[Unwinder]

And of course, the most likely possibility is that RivaTuner is making a mistake in wrongly interpreting register values as a quad "locked on the hardware level and cannot be unlocked"...

Don't think so. Pixel pipe related bits of pipe config register are unified for whole NV4x family, each pixel pipe state is controlled by the corresponding bit, the difference between NV4x (e.g. between NV40 and NV47) is only the amount of bits in use (e.g. bits 0-5 for NV47, bits 0-4 for NV40 etc), determining the maximum amount of pixel pipes in chip.
12 pixel pipes of our NV4B (G73) sample were enabled by bits 0-3 1011b, bit 2 was hardwired to 0 (typical for hardware masked pipes seen in the previous NV4x chips). I see zero reasons for using such pipe control scheme in 3-quad chip and mixing unused bits with used ones. I'm under strong impression that there is something reserved (unused).

 

[Ailuros]

For one it would give me a more reasonable explanation of the relatively high chip complexity of G73.

I wouldn't be surprised if we'd see 4 quad G7x@80nm in H2 06' to counter RV560. Of course is it all speculation from my behalf.

 

[dizietsma]

Judging by past history it is unlikely that Unwinder is wrong on the matter, however I suppose things could have changed or there is another explanation.

 

[Fodder]

... but it's so small!

Either someone's made a mistake, or NVIDIA's engineers are even brainier than we thought.

 

[chavvdarrr]

its quite simple to check:
see values of the bits from several G73 cards, if the mask is different (1011, 1101, 0111, 1110) then it has 4 quads by design.
If mask is always same, perhaps this is not the case

 

[MuFu]

Don't think so. Pixel pipe related bits of pipe config register are unified for whole NV4x family, each pixel pipe state is controlled by the corresponding bit, the difference between NV4x (e.g. between NV40 and NV47) is only the amount of bits in use (e.g. bits 0-5 for NV47, bits 0-4 for NV40 etc), determining the maximum amount of pixel pipes in chip.
12 pixel pipes of our NV4B (G73) sample were enabled by bits 0-3 1011b, bit 2 was hardwired to 0 (typical for hardware masked pipes seen in the previous NV4x chips). I see zero reasons for using such pipe control scheme in 3-quad chip and mixing unused bits with used ones. I'm under strong impression that there is something reserved (unused).

Could it be something to do with a revised redundancy scheme? E.g. high bits in the register now represent active paths through working functionality, and low bits mask everything else (as configured by I/O multiplexing; in contrast to discrete quad masking). I am not sure if they have implemented this system yet, but it's an possible explanation for G73 appearing to have additional units.

 

[Ailuros]

G73 has 3 quad pipes (12 fragment pipes). Sorry to disappoint.

Dagnabit. How on earth did I overread that comment? Note to myself: read before you write

 

[Unwinder]

its quite simple to check:
see values of the bits from several G73 cards, if the mask is different (1011, 1101, 0111, 1110) then it has 4 quads by design.
If mask is always same, perhaps this is not the case

True if blocked pipes (if any) are faulty, false if they are hidden due to marketing issues.

 

[Unwinder]

Could it be something to do with a revised redundancy scheme? E.g. high bits in the register now represent active paths through working functionality, and low bits mask everything else (as configured by I/O multiplexing; in contrast to discrete quad masking). I am not sure if they have implemented this system yet, but it's an possible explanation for G73 appearing to have additional units.

AFAIK, there is still 1 bit in control register -> 1 pipe mapping. It is very easy to check, new (beta) version of NVStrap driver is able to disable pipes on G71/G73 by masking the corresponding bits.

 

[Geo]

its quite simple to check:
see values of the bits from several G73 cards, if the mask is different (1011, 1101, 0111, 1110) then it has 4 quads by design.
If mask is always same, perhaps this is not the case

That was my thot as well. I suppose it would be possible with some flummery to have that happen downstream a bit so that the off quad is always in the same bit position, but there wouldn't be much reason to do so if you're going to allow it to report at all.

So now we need, oh 4 or 5 anyway, people to try it on their G73 and see if there is any variation. Certainly enuf reviewers around here have it and can settle that point (i.e. if there is variation in which bit is turned off).

 

[MuFu]

AFAIK, there is still 1 bit in control register -> 1 pipe mapping. It is very easy to check, new (beta) version of NVStrap driver is able to disable pipes on G71/G73 by masking the corresponding bits.

So have you tried all the 4-bit permutations for G73? Edit - your sample, that is.

 

[Unwinder]

So have you tried all the 4-bit permutations for G73?

I've neither G71 nor G73 in my testrigs, I can only rely on Digit-Life/iXBT testers.

 

[MuFu]

Deleted my first post on this because I thought they were PWM regulators, but if you look at the group of (Infineon) MOSFETs in the top right corner of the 7600GT reference board, there's a set of pads free for a 4th and mouting holes for a heatsink. None of the review samples (not even the Superclocked and XXX editions) have this additional FET, but the official nV slides show it.

I just wonder if they've designed in support for a higher spec SKU through an additional power phase and better cooling. Could just be an option for AIBMs though - or something that the board managed to pass VV&T without.

 

[trumphsiao]

Deleted my first post on this because I thought they were PWM regulators, but if you look at the group of (Infineon) MOSFETs in the top right corner of the 7600GT reference board, there's a set of pads free for a 4th and mouting holes for a heatsink. None of the review samples (not even the Superclocked and XXX editions) have this additional FET, but the official nV slides show it.

I just wonder if they've designed in support for a higher spec SKU through an additional power phase and better cooling. Could just be an option for AIBMs though - or something that the board managed to pass VV&T without.

177M transistor counts comprise of 4 Quad Pixel Shaders and 4 Dispatch processors which seems to be amazing if it really does