Fusion die-shot - 2009 Analyst Day

[hkultala]

I guess the questions are based around how good Llano is on the 32nm node and how they can mitigate the issue of bandwidth. Obviously their desktop GPU line is getting progressively better and I suspect that the earliest Fusion CPUs will be 2 core + GPU models so that ought to make the cache model a little more friendly.

Your suspections have very little to do with what is actually happening, the released information tells quite different story.

Llano has 4 cpu cores, and Llano prototype chips are already distributed to some 3rd parties (like motherboard manufacturers etc). There have been llano die shots published.

AMD is not going to cripple away 50% of it's cpu cores when it's releasing the product.

The cache model that they are using is the best solution for fusion; Having common L3 cache with GPU and CPU would not help at all, the GPU would just pollute the cache and prevent the CPU to get any performance improvement from it.

 

[Jawed]

Has there been a shot of the entire Llano die?

 

[mczak]

Why wouldn't it make sense to share the L2 (not the entire cache, just a subset)? I don't know much about Llano's L2.

Well, the cpu part is supposed to be like any other K10. Hence L2 is separate to each core (and exclusive to L1). I think it would be very, very odd to have parts of the cache from each core usable by the gpu in this cache hierarchy.

 

[Alexko]

Has there been a shot of the entire Llano die?

Just that low-res blurry one, as far as I know:

 

[Jawed]

Which doesn't have L3.

 

[fellix]

Just that low-res blurry one, as far as I know:

This one is the best available for now. Not sure it's a complete die area shot -- the perimeter seems to be cropped a little.

 

[Jawed]

For what it's worth I'm assuming that AMD is hiding part of the die, which is why I asked if there's a full die shot out there.

On the other hand, does performance matter?

 

[nAo]

For what it's worth I'm assuming that AMD is hiding part of the die, which is why I asked if there's a full die shot out there.

On the other hand, does performance matter?

If that die picture indicates that ~half of the die is devoted to graphics (not sure, it's too small..) then I'd say that AMD thinks gfx performance matters.

 

[stef]

There are better quality pictures:

 

[stef]

and:
http://chip-architect.com/news/Llano_comp2.jpg

 

[fellix]

Those two shots are quite photochopped over and over again.

The clarity on this matter is still to no avail. Just wait for something more complete.

 

[Jawed]

If that die picture indicates that ~half of the die is devoted to graphics (not sure, it's too small..) then I'd say that AMD thinks gfx performance matters.

Maybe they're pad/perimeter limited

Seriously: for any kind of performance it seems to me there's two choices:

1. GPU partakes of the CPU cache hierarchy - L3 or L3/L4
2. there's a pool of "GPU-dedicated" off-die memory (and an interface we can't see) which the CPU can access through the GPU's memory controllers - the GPU's L2 peering with the x86 L2s, effectively.

The latter would be a partitioned address space. For a consumer-only CPU this would be fine, as it's not going to be kitted out with hundreds of GB.

Would option 2 be like Xenon/Xenos in XB360 (have they merged into a single die yet? The GPU is basically the northbridge in that setup)? Two pools of memory, but not a teeny pool for render targets.

And before you know it, you can ask "is this chip/concept destined for a console, too?". Maybe that question's been asked in the Console Forum...

Jawed

 

[no-X]

This one is the best available for now. Not sure it's a complete die area shot -- the perimeter seems to be cropped a little.

This one is different to the other ones. Units in the GPU section and their layout reminds me RV7xx. The other Fusion dieshots are different, one type of unit seems to be missing there (interpolators?). It also shows 240SPs, while the newer one shows 300 SPs...

 

[fellix]

They are all the same, with the exception that the green-ish one is more complete and clear. As I said, all the others are photochopped more or less, in an attempt to do some loosely patched guesswork.

 

[Kaotik]

http://www.techeye.net/chips/global-foundries-12-inch-wafers-to-take-on-tsmc

According to GloFo, Llano is already in production on 32nm process

 

[Squilliam]

http://www.techeye.net/chips/global-foundries-12-inch-wafers-to-take-on-tsmc

According to GloFo, Llano is already in production on 32nm process

Tape out is usually 12 months ahead of release isn't it for CPUs? Its unlikely we'll see the future until next year.

 

[Psycho]

Look at the first post in this thread then - 12 months should be from october/november

 

[Lightman]

Look at the first post in this thread then - 12 months should be from october/november

In line with what sources/AMD were saying a year or more ago.
So either they needed significant respin which pushed things back a bit or this is intentional to build up stock before release.

 

[Kaotik]

In line with what sources/AMD were saying a year or more ago.
So either they needed significant respin which pushed things back a bit or this is intentional to build up stock before release.

Or just the process not being ready for production earlier

 

[rpg.314]

http://www.semiaccurate.com/2010/06/01/amd-show-fusion-tomorrow/

Fusion peep show set for tommorrow.