Fusion die-shot - 2009 Analyst Day

Guys, go to the full video and listen to what the presenter is saying.

"Can you imagine this sort of performance in a Netbook this size?"

It could be Ontario. :oops:
 
I hope they integrate CPU+NB+SB, all into one die.

I'm not sure that would be such a great idea. Southbridges contain a lot of I/Os, and I'm not sure they would mix very well with the rest, process-wise.

As I understand, there are trade-offs involved when making a SoC, and while those are acceptable for very low-power applications (tablets, smartphones, etc.) they may not be for netbooks or thin & light notebooks.
 
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*counting*
 
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I get 35x32 dies across two axes on a quick count. Call the dies 8.8mm per side (77mm²), that's about 840 dies per wafer.
 
I'm not sure that would be such a great idea. Southbridges contain a lot of I/Os, and I'm not sure they would mix very well with the rest, process-wise.
SB's are fabbed with older logic processes just fine.

As I understand, there are trade-offs involved when making a SoC, and while those are acceptable for very low-power applications (tablets, smartphones, etc.) they may not be for netbooks or thin & light notebooks.
How much I/O do you need in netbooks? 2-3 USB ports, 1 sata port, some audio, anything else? How much does that take? 20 pins?

AFAIK, the LCD driver would have been in NB earlier. I am not sure where will it be placed now.

WiFi/Ethernet will have separate chips obviously.
 
So, the AvP DX11 demo was actually run on the low-power APU variant, not the full-featured Llano? That's even more impressive!
 
SB's are fabbed with older logic processes just fine.

How much I/O do you need in netbooks? 2-3 USB ports, 1 sata port, some audio, anything else? How much does that take? 20 pins?

AFAIK, the LCD driver would have been in NB earlier. I am not sure where will it be placed now.

WiFi/Ethernet will have separate chips obviously.

I agree, a SoC can host the needed I/O ; actually next to me is sitting a netbook using an x86 SoC.
While Wifi is on internal USB, the ethernet controller is part of the SoC along legacy, USB, audio, IDE (with a SD card to IDE feature) and VGA ;)

http://www.xcore86.com/site/sites/default/files/Xcore86 Block Diagram V10-1.png

but they're using 90nm, and it doesn't have the performance and 3D acceleration of a Atom + intel graphics notebook for sure; but it's cheaper and lower power.
 
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so this must be 32nm? :oops:
Noone ever doubted Ontario/Llano will be 32nm, so why the surprise?
(edit: oops looks like Ontario is 40nm...)

So, the AvP DX11 demo was actually run on the low-power APU variant, not the full-featured Llano? That's even more impressive!
I dunno I'm sceptical. While that netbook quote seems to point that direction, the fact they didn't mention if it was Llano or Ontario leads me to believe it is Llano...
FWIW, I'm still a bit wondering why Ontario and Llano appear to be scheduled to arrive at about the same time. Since Llano is "only" pretty much the integration of existing K10-quadcores and Evergreen-class DX11 GPU (presumably), but Ontario additionally uses the new Bobcat core. Also, there have been die shots, transistor count estimates etc. for Llano, but nothing the like (so it's impossible to tell how much the GPU has been cut back) for Ontario.
(actually, even stranger, so Llano is old cpu but new manufacturing whereas Ontario is "old" manufacturing but new cpu...)
 
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