The control logic blocks are identical function-wise, despite looking a bit different each other -- that is due to the extensive use of automated process for optimal placement instead of hand-tuned circuits, used only for the critical parts.nor identical otherwise wrt control logic (the "non-yellow-part").
Might also be worth correlating with the GPU being "replaced", e.g. G94 being replaced by GT215 (GTS260M), since it seems likely that the package sizes are the same.Would it be fair to assume that the substrate on these are the same size, or at least for the 260 and RV740, which are both 128bit, gddr5 etc?
Nope, NVidia's being shy about ROPs and TMUs. ROPs scale with bandwidth and theoretically the smallest of these chips, GT218, has a single cluster of 16 ALU lanes, so prolly has 8 TMUs.And do we have any hard info on the number of ROPS in GTS260M?
Ooh, that's nice.Just for fun...
Looking at the die and package shots nvidia provided for G210m(under additional images) here, can see die is almost exactly 1/3 the package size.
Back in January vr-zone had a gt218 P692 (GDDR3?) board which via PCI-E specs gave the package size as 22.6x22.6mm. Which implies the die size is 22.6mm / 3 = 7.67mm or 58.8mm2 die area for the G210m.
Similarly fudzilla reckon the package size for the GT216 was 29mm. Looking at the GT240m that is also almost exactly 33% width and length of package size implying 29 x 0.33 = 9.66mm for die sides => die size of GT240m is 93mm2
Aha, that's pretty cool, though this caveat does screw things up.Obligatory caveat about the laughable reliability of this calculation: by constant pin separation the GTX280m is 2.87x the G210m size ie 167mm2 or a third less than it actually is in real life
Redoing the calc i get the same as above. Also 54.8mm2 for G210m. Originally i did it only using shot of the 2 chips one face up and one face down both of which were at different angles, tried hard to account for the perspective guess i slipped up somewhere though.For what it's worth, I get a different size for GT216, using the "additional views" pix from NVidia. Assuming the package is 29mm on each side, the chip is indicated to be 10.1mm per side, 102mm²
It seems to me that GT215 has the same package size as the balls are exactly the same. This leads to 11.9mm per side, 141.6mm².
If we assume 0.5mm of die encapsulation, then these come out as 92mm² and 130mm².
It looks like the PCIe Phy interface is damn hard to scale than anything else.I think fellix's ideas are on the right track, though the "stacked" stuff is quite a puzzler.
Apart from this maybe not being very accurate: In the GT200-Shots, there's two vertical units "above" each set of processing cores - AFAIK that was scheduling/control and the two quad-TMUs attached to each SIMD. Those are missing in the 40nm shots altogether and the control-part is attributed to "texture" in the picture from techreport.Carsten if you compare with the annotated GT200 here (even if there are some who doubt its accuracy):
http://www.techreport.com/articles.x/14934/2
Which you were one of the greatest critics of, IIRC.you should see that TMUs and ROPs take up acres of space.
I should have said I think PCI Express is that long thin section down the left hand side - compared with other die shots, PCI Express is thinner than DDR.
That stacked stuff might be GDDR5-specific. I dunno.