Don't get fooled by .... nvidia attacking Ati

Discussion in 'Graphics and Semiconductor Industry' started by nagus, Sep 24, 2004.

  1. nelg

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    EE times is not a consumer publication so any misleading articles published therein would have minimal impact on sales. Amongst the readership of EE times, those who’s reading of misleading or incorrect information would have a material effect on ATI’s sales most likely would have been contacted by ATI directly.

    Even having a successful lawsuit against them would be potentially more detrimental than ignoring the mistake. In every conflict, irrespective of the conclusion, there are those who will disagree. Such a law suit would certainly make all the mainstream business news and even if only a small portion of those readers did not trust the conclusion then fallout would be much greater than ignoring it in the first place.
     
  2. FUDie

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    You still have yet to provide proof of this.
    Completely irrelevant to the discussion at hand.

    -FUDie
     
  3. hovz

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    lol fan..boys are taking over this forum
     
  4. Pete

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    Well, they *did* release a card that worked with DDR-II. Did they specifically say they'd work in DDR-II mode, or just that their GPUs could work with DDR-II?
     
  5. Beafy

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  6. PatrickL

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    Don't bother, if i can use an image we say in my area :
    "One can't make drink a donkey that is not thirsty".
    Radar perfectly fits the job :)
     
  7. DarN

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    Did you hear that radar? Ignorance or denial of reality.
     
  8. radar1200gs

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    God you fanATics crack me up. At least nVidia supporters can admit nVidia lied.

    But don't mind me:

    QUACK was "an unfortunate accident"

    ATi had a fully functioning DDR-II card before nVidia

    There are no Trilinear cheats in ATi's drivers

    and the sun shines out of ATi's corporate arse.
     
  9. Mariner

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    I've completely lost track of the point of this argument.

    Just let radar think whatever he likes about ATI/NV - nobody is going to change his mind, whatever evidence/lack thereof is produced. :)
     
  10. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    Suing a publication is always you last port of call since it inevitably brings worse publicity to you than anyone else; it is always a last resort.

    However, OK, we have EE Times quoting "sources", but we have the benefits of history now, so let’s take a look.

    The sources claim that "The part was not designed for use with DDR-II". Well, clearly, from an architectural standpoint it was since 9800 shipped with DDR2 RAM - I've yet to hear anyone claim that the shipping 256MB PRO's are running in compatibility mode.

    Now, before you say "Yes, but 9800 was a different chip with architectural changes", that’s correct and incorrect - R350 did have opportunistic tweaks and changes, but nothing massive from an architectural point of view, the main benefits came from moving to a slightly different process. Its also pretty easy to tell that there were no major architectural overhauls to the memory bus between R300 and R350 since the issues with DDR2 were already apparent at when it was being respun, and rather than add support for DDR2 they would have sorted out the major issue with R300's memory bus which was getting it to operate at high frequencies - to this day the highest speed an R300 design has shipped at is on the memory is 365MHz; faster DDR(1) RAM was already available by the time it was released. If they were going to make changes to the memory bus then adding DDR2 support would not have been the priority, sorting out the bus to operate higher than the ~300-365MHz range would have been. I'd say its fairly easy to surmise that the running in DDR2 mode was already in place, the issue was that their bus doesn't really run operate at speeds that a beneficial to use DDR2 with as it couldn’t actually run at the maximum frequencies of DDR at the time (the reason for using it on the 256MB PRO was opportunistic in terms of cost and also probably a little element of PR coup).

    With NV3x (GF-FX) there is a one to one relation between pixel and shader pipelines - there was never more than 4 shader pipelines in any of the NV3x designs.
     
  11. Unit01

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    Radar are you really that desperate to bump your postcount?
    you make countless posts that contain 2-3 lines of bla bla bla ATI is evil NVidia is good, ati only does bad, nvidia only does good. Most people here see the pattern of your posts. It's not necessary for you to post anymore. It's already known that if you were to post it would be like all your other posts, which are ATI evil, Nvidia good.
     
  12. radar1200gs

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    With shaders and NV3x you are forgetting that partial precision allows you the equivelant of 8 shader pipes (with the provision that they are SIMD, 2 fp16 virtual pipes in 1 fp32 real pipe and only the 4 real pipes can execute different (instruction wise) shaders). Of course only 4 results from the shaders will be output as pixels in any one cycle.

    About the memory speeds, that could be why ATi ran the memory in DDR-1 compatability mode, i'm not certain (I'd have to reread the DDR-2 specs but I'm certain anything under 400mhz is considered to be DDR-1).

    Of course a lawsuit would bring negative publicity. Just another reason why intelligent companies avoid presentations/announcements etc that could open them up to the possibility of a lawsuit in the first place.
     
  13. radar1200gs

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    Trust me when I tell you: I'm not here to win a popularity contest or bump post counts or anything remotely like that...
     
  14. Dave Baumann

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    Again, you would be incorrect. The ALU's themselves can only operate on a single fragment (pixel) per cycle, they could not increase that by using FP16. A single FP16 instruction fundamentally executes at the same speed as FP32 in NV3x, the performance improvements primarily come from the register space which allowed NV3x to have more pixels in flight when using FP16 register space than FP32 - I believe that there was actually one instruction in NV35 that would take two cycles to operate in FP32 rather than FP16.

    However, that makes no difference since instructions don't necessarily equate to fragments (pixels) since you are often executing many instructions on a single pixel. The fragment pipeline could only work on a single quad of pixels in paralell at any time; the only time that NV30/35 operated on two quads was in Z/Stencil mode which bypasses the fragment shader.

    AFAIK its the termination and signalling thats important (but I've not read the specs).
     
  15. radar1200gs

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    What do you think registers and register space are Dave? By splitting an Fp32 register in half you double the register space. But you can still only output 4 pixels per cycle.
     
  16. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    Its a pipeline - the size of the register requirements effects the number of pixels in flight within that pipeline, not the number of pixels that are exectuted in parallel. Only a single quad of pixels are ever executed in parallel.
     
  17. radar1200gs

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    Yes I know that. There are only 4 ROPs each tied to a 32 bit main pipe. So only 4 pixels can be produced per cycle.

    however with fp16 8 shader results can be computed per cycle.

    NV3x then outputs the entire fp32 register to the ROP (if you are using full precision) or the top or bottom half for FP16 (I don't know if the chip can choose which half to send per cycle - I'm guessing that it something that was probably intended but never worked correctly).

    This setup is good for math intensive shader scenarios, obviously not so good if you want maximum pixel throughput.
     
  18. Dave Baumann

    Dave Baumann Gamerscore Wh...
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    Clearly you didn't understand whats being written

    No, per ALU, only 4 instuctions can be executed in either FP16 or FP32.

    The register space issues affects the number of pixels being executed serially.
     
  19. Unit01

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    Don't know if you have time, but do you think you could provide a link to the DDR-II specs?
     
  20. radar1200gs

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