DM's 65 nm transistor density analysis based on Sony EE data

[asicnewbie]

> You have to add the cach line tag(4 byte per 128 byte cache line?) and control logic. The "tax" is about 10%~15% to the number.

And aren't large SRAM-blocks built with redundant (spare) arrays for manufacturing defect management? I know DRAM ICs have some spare rows/columns for defect-repair purposes (much like how hard drives are manufactured with more physical sectors than their official capacity rating.)

The overhead could add another 5-10%, perhaps?

 

[Saem]

Indeed they are. The overhead of course, depends on the IC. From my understanding, from their test runs they figure out what sort of yields they're getting on the SRAM and then add it.

I've never heard any figures as to how much this usually means.