Awesome work!Yes, if you have one of the chips I encourage you to try it out
DX12 is the API-Library, the Feature-Levels are simply definied within the API.
Andy, wrong Ryan!I think we have to leave that to the press for a few reasons, if it even makes sense. Ryan Shrout was considering something like that earlier in the thread.
FWIW - there's no such thing as "DirectX 12.1" for starters
Whoops, good pointAndy, wrong Ryan!
Anyhow, the idea is still a WIP. Hard to find the time between Skylake and IDF, but it's definitely something I want to get done.
In any case I agree with your earlier assessment that it's unclear whether it's a benefit to consumers to bring this topic up or not, but you're better qualified to decide than I am In any case now you have some additional information to work from on the Intel side.
No, not yet. Can try tomorrow (edit: darn, in a few hours later this day...) when I'm back at my Haswell/Windows 10 rig at the office.
That's not a problem at all, feature level it's just an enum name for the DDI...Awesome work!
I'm really curious about the technical details on the next IDF.
Maybe some details about the difficulties coming with implementing all DX12 features.
DX12 is the API-Library, the Feature-Levels are simply definied within the API.
In the future we could get an API-Update to DX12.1, introduction the new FL12.2 and then everyone who wrote FL12.1 = DX12.1 will get a problem.
typedef
enum D3D_FEATURE_LEVEL
{
D3D_FEATURE_LEVEL_9_1 = 0x9100,
D3D_FEATURE_LEVEL_9_2 = 0x9200,
D3D_FEATURE_LEVEL_9_3 = 0x9300,
D3D_FEATURE_LEVEL_10_0 = 0xa000,
D3D_FEATURE_LEVEL_10_1 = 0xa100,
D3D_FEATURE_LEVEL_11_0 = 0xb000,
D3D_FEATURE_LEVEL_11_1 = 0xb100,
D3D_FEATURE_LEVEL_12_0 = 0xc000,
D3D_FEATURE_LEVEL_12_1 = 0xc100
} D3D_FEATURE_LEVEL;So Haswell is the only GPU without TiledRes support? Even the old low-end HD 7700 GNC support them. But yes, I understand that 31 bit virtual address limit is quite awful.
Thanks, but Andrew Lauritzen already solved the mystery
Come to my talk if you're at IDF
I'm sure slides will be posted otherwise. To be fair it's more about DX12 API and how you can use it to efficiently use Gen9, but there's a little bit on new features in there too and some overlap.What time (and what's the session number) for your talk?Come to my talk if you're at IDF
Does that means that Fermi or GNC 1.1 cards can have ROVs and CR ? What is needed for cards based GCN to support these resources ?
I greatly would , if i were a journalist or developer, but I'm just a guy who is commonly interested in this topic.Come to my talk if you're at IDF
A certain degree of hardware support of course.
No. It means that important features can be implemented independently of feature levels. In case of CR and ROV, vendors don't need to support a full feature level 12_1 - they can just expose these two features while supporting maximum feature level 11_1, as Intel did.
It's because this thread is about feature levels, while multi-engine is neither a part of any feature level nor an optional capability.
For completeness`s sake anyway:Thanks, but Andrew Lauritzen already solved the mystery