geo said:http://www.theinquirer.net/?article=23593
Here's the actual article. Thinking back on Josh's interview with NV, maybe they're after making the pcie connection wide enough to do away with the intra-card connector without impacting performance? Folks might like that. Don't know what it would do to compatibility, if anything.
I had a good read of that linked thread last night and again this morning, since we've had some Crossfire numbers for a while that I'm now thinking about writing up.
It's geo's quote about using unused PCIe lanes for the inter-GPU communications that's been bugging me, as I think about SLI, any possible 'SLI2', and Crossfire as a whole.
The PCI Express specification dicates you negotiate 1x, 2x, 4x, 8x, 16x or 32x lane appropriation when the devices talks to the root port and announces itself on the bus. Following on from those lane bundles, they're the only electrical slots you can have, too.
So to appropriate spare lanes in a PEG16X slot just for inter-board communications, that means a new set of mainboards that put 8X from the slots to the root port, for normal working, and the back 8 lanes from the slots are routed to each other, for the cards to talk over. That's the first lane split you can do with a PEG16X slot, since there's no way to negotiate say the first 14 lanes, then just rebundle the back 2. It's a power of 2 for splits and reassignment.
And if 8 lanes are being pushed that way, each GPU would need another PCI Express controller that also acts as a pseudo root port, as far as I can tell, so the negotiation can be made, unless there's some extra logic on the mainboard that isn't there just now.
In addition, pushing that data over PCI Express, as Xmas has said I think, doesn't guarantee any explicit timing of the transfer of data, so you can't rely on information arriving within a certain time frame. And timing of buffer pushes and whatnot would likely have to be as tightly controlled as possible. Hence the custom Xylinx FPGA on ATI's boards, for controlled composition.
I think it's more likely that the connecting bus that currently exists between the two boards will just get faster and/or wider, and we'll continue to see it for any SLI2 implementation that maybe needs a bit more bandwidth on that connector.
As long as the inter-GPU connectors continue to be bundled with either graphics board (buying two graphics cards and having a spare connector wouldn't be the worst thing in the world, I think) or mainboard as they are now, I don't see the big problem with connecting the boards up that way for the forseeable future and a further generation of SLI.