Re: ...
nondescript said:
DeadmeatGA said:
nondescript
Let me illustrate my point.
A Radical architecture : CS301
- 42 million transistors
- 72 mm2
- 200 Mhz
- 25 GFLOPS peak
- 0.13 micron IBM SOI process
A traditional architecture : PPC970
- 52 million transistors
- 121 mm2
- 2 Ghz
- 16 GFLOPS peak
- 0.13 micron IBM process
[...]
High clock speed is a design feature and not a process feature. For EE3 to clock at 4 Ghz, SCEI would have to superpipeline the PPC core and VU to 20+ stages at the cost of massive transistor count bloat.
Hey DMGA, I'll respond in full to your post tomorrow - kinda busy today - but yeah, I understand where you're coming from.
Here we go:
Let's look at another architecture - the P4 Northwood core - something the Xbox CPU is much more likely to look like, and much more similar to a traditional PC architecture.
Pentium 4 Northwood 3.06GHz
.13-micron
146mm square
55 million transistors
6.12 Gflops peak
Instead of describing it myself, here's a link to Hannibal's excellent and accessible description of both the G4e (PPC) and P4.
http://arstechnica.com/cpu/01q2/p4andg4e/p4andg4e-2.html
Key points (I cut out some stuff to keep the length reasonable):
The G4e breaks the classic, four-stage pipeline into seven stages in order to allow it to run at increased clock speeds on the same manufacturing process. Less work is done in each of the G4e's shorter stages but each stage takes less time to complete. Since each stage always lasts exactly one clock cycle, shorter pipeline stages mean shorter clock cycles and higher clock frequencies. The P4, with a whopping 20 stages in its basic pipeline, takes this tactic to the extreme.
As we'll see, the Pentium 4 makes quite a few sacrifices for clock speed, and although Intel tries to spin it differently, an extraordinarily deep pipeline is one of those sacrifices.
The drastic difference in pipeline depth between the G4e and the P4 actually reflects some very important differences in the design philosophies and goals of the two processors. The G4e's approach can be summarized as "wide and shallow." Its designers added more functional units to its back end for executing instructions, and its front end tries to fill up all these units by issuing instructions to each functional unit in parallel. In order to extract the maximum amount of instruction-level parallelism (ILP) from the (linear) instruction stream the G4e's front end first moves a small batch of instructions onto the chip. Then, its out-of-order (OOO) execution logic examines them for interdependencies, spreads them out to execute in parallel, and then pushes them through the execution engine's nine functional units. Each of the G4e's functional units has a fairly short pipeline, so the instructions take very few cycles to move through and finish executing.
At any given moment the G4e can have up to 16 instructions spread throughout the chip in various stages of execution simultaneously. The end result is that the G4e focuses on getting a small number of instructions onto the chip at once, spreading them out widely to execute in parallel, and then getting them off the chip in as few cycles as possible.
The P4 takes a "narrow and deep" approach to moving through the instruction stream. It has fewer functional units, but each of these units has a deeper, faster pipeline. The fact that each functional unit has a very deep pipeline means that each unit has a large number of available execution slots and can thus work on quite a few instructions at once.
It's important to note that in order to keep the P4's fast, deeply pipelined functional units full, the machine's front end needs deep buffers that can hold and schedule an enormous number of instructions. The P4 can have up to 126 instructions in various stages of execution simultaneously. This way, the processor can have many more instructions on-chip for the out-of-order execution logic to examine for dependencies and then rearrange to be rapidly fired to the execution units.
As we can see, in either case, the bulk of the pipeline is not the execution itself, but the stages before and after - in both cases, traditional processors devote significant transistor budgets to speculative processing, examining interdependencies, and other structures to support parallel processing of essentially serial code. In Hannibal's words, "to extract the maximum amount of instruction-level parallelism (ILP) from the (linear) instruction stream."
In the P4, five stages are used to fetch instructions from the L1 cache and the Branch Processing Unit, including one stage that does nothing but wait for signals to arrive. Seven stages are used to process and direct out-of-order execution. Two more stages to actually send the signal to the processing units. Two more to get into the registers of the execution units. One stage to execute. Three more stages to verify and reorder the results. 20 stages total.
CELL will need some pipelining, since the cores will be running much faster (2x-8x) than the memory, but it will be nothing like the P4 - the jobs are inherently different. Graphics and physics processing are highly and easily parallel. Just look at the design of a modern GPU. My guess is the PPC cores will handle the inherently linear code, using the process described above, while the bulk of the graphics and physics processing will be done by the highly parallel architecture similar to the Clearspeed chip - that, as I hope I've shown, does not need such elaborate pipelining.
Last bit:
I agree that 1Tflops will be very hard to achieve. 1Tflops is a number that shouldn't be tossed around lightly, and I'm not about to stick my neck out and say CELL will be 1Tflops, or that the PS3 will be 1Tflops. But I think it is possible, and I don't think it is an overestimation to say that STI is capable of a 1Tflops processor.
