zidane1strife
Banned
I too doubt it will be 1Tflops...
indeed...
ed
Clearspeed announces CELL-like processor
- Thread starter nondescript
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I too doubt it will be 1Tflops...
indeed...
ed
The powerconsumption of desktop processors is also projected to be well over 100 Watt by that time, and desktop processors have a far lower average switching frequency than Cell (I think Sony could get away with a 100 Watt processor, but some significant surface area of the outer case will need to consist of cooling fins ... and I dont know wether large heatpipes are cheap).
Re: ...
On a higher level the difference between how Cell works and how an ATI card works should be very obvious. On a lower level, Cell (as I understand it) is a group of processor cores, split into clusters, split into execution units. These elements do not share resources such as registers or ALUs, but each independantly work on a "cell" of data.
On a high level a unified shader model is just an implementation detail of the API. On a low level ILDPs like R500 allocate hardware resources as needed by the program, rather than feeding clusters of instructions through static function units (as Cell apparently does).
If you think in such abstract terms, you can also say Cell isn't that much different from a digital watch (they both use electricity) or an apple (they both are constructed with atomic particles). The key difference here is that Cell does not contain anything like a hardware graphics pipeline, the graphics pipeline is the software you feed it (if that is what you feed it, Sony intends to use this architechture in a wide range of devices). Any graphics card available today or in the next few years is the reverse (you won't find a GeforceFX or an R500 in a Walkman).
I don't see your point here. 3dfx Voodoo, which was very much a fixed-function platform, also increased performance through driver revisions, and performed much better using its own API (Glide) than Direct3D. This is simply due to the fact that Direct3D is a high level API, "compiled" on the fly by the driver for the target hardware, meaning there is a huge capacity for waste.
Vince said:Josiah said:
How does Cell not "share resources". You can run anything from Physics to basically any Shader program. It's the exact embodiment that, on a high-level, we'll one day see PC IC's processing.
To say that a Unified Shader is unlike what you can do with Cell is like saying that Icing doesn't work on Cake.
On a higher level the difference between how Cell works and how an ATI card works should be very obvious. On a lower level, Cell (as I understand it) is a group of processor cores, split into clusters, split into execution units. These elements do not share resources such as registers or ALUs, but each independantly work on a "cell" of data.
On a high level a unified shader model is just an implementation detail of the API. On a low level ILDPs like R500 allocate hardware resources as needed by the program, rather than feeding clusters of instructions through static function units (as Cell apparently does).
Vince said:
If you think in such abstract terms, you can also say Cell isn't that much different from a digital watch (they both use electricity) or an apple (they both are constructed with atomic particles). The key difference here is that Cell does not contain anything like a hardware graphics pipeline, the graphics pipeline is the software you feed it (if that is what you feed it, Sony intends to use this architechture in a wide range of devices). Any graphics card available today or in the next few years is the reverse (you won't find a GeforceFX or an R500 in a Walkman).
Vince said:
I don't see your point here. 3dfx Voodoo, which was very much a fixed-function platform, also increased performance through driver revisions, and performed much better using its own API (Glide) than Direct3D. This is simply due to the fact that Direct3D is a high level API, "compiled" on the fly by the driver for the target hardware, meaning there is a huge capacity for waste.
No i noticed it then too . I just felt like being sarcastic about the only thing ruining sonys plans is an act of god. Because it really don't matter if they pumped all the money in the world into the cell chip. IT could still easily fail.Panajev2001a said:jvd said:
I posted the same ind of news ( only with links to Sony's own site ) a while ago and jvd notices it now ?
This was all present in Sony's IR website for a good while and I have repeated over and over the $4 Billions invested in CELL R&D and the $4 Billions invested for Semiconductor R&D all over the course of the next three years.
no recognition for the good ol' Panajev
I like Vince's link as it puts, one more time, CELL together with PlayStation 3 even though I would think that by now there would be no doubt about that
CELL will not be only used for PlayStation 3 and that investment is needed to help Sony save money in the future and mantain their competitive edge technologically wise: if CELL and other chips produced thanks to these investments allow Sony to produce most of the ICs it now buys from third parties ( $2+ Billions worth of ICs each year ) the whole R&D investment will kinda pay for itself if you think about it.
I can definately see Josiah's point.
Having read a few articles and lectures slides from universities about reconfigurable computing, I think his description of Cell being FPGA isn't far off. There are actually a few proposed academic designs which are reminescent of Cell, which are designed to optimise themselves to a certain task by effectively allocating it's processing elements via software for whatever tasks are thrown at it. This is where Josiah seems to hit the nail squarely on the head and where you (Vince) seem to be missing his point.
Now the NV3x and so on, are different. As Josiah said, you can change the allocation mechanism (software) in cell and have it reconfigure itself for various tasks. What josiah is saying is that in NV3x et al, this is not the case. Here you have a fixed hardware unit which looks at in comming data (instructions + information) to work on.
The other side of the argument is that Cell isn't reconfigurable since the execution resources are static in their definition. The thing to note here is that this is more granuality and sharing can be facilitated if need be.
The unified shading architecture will likely differ a fair bit from Cell. Cell will approach matters in running software to deal with the way software will run on the machine. While the graphics architectures will use hardware to run the software on the machine. Of course, there will eventually be microcode programming et al and finally the two approaches will converge.
But the level of abstraction that Josiah is talking about is definately less abstract and his points remain quite valid. I have yet to see a good argument to the contrary.
Having read a few articles and lectures slides from universities about reconfigurable computing, I think his description of Cell being FPGA isn't far off. There are actually a few proposed academic designs which are reminescent of Cell, which are designed to optimise themselves to a certain task by effectively allocating it's processing elements via software for whatever tasks are thrown at it. This is where Josiah seems to hit the nail squarely on the head and where you (Vince) seem to be missing his point.
Now the NV3x and so on, are different. As Josiah said, you can change the allocation mechanism (software) in cell and have it reconfigure itself for various tasks. What josiah is saying is that in NV3x et al, this is not the case. Here you have a fixed hardware unit which looks at in comming data (instructions + information) to work on.
The other side of the argument is that Cell isn't reconfigurable since the execution resources are static in their definition. The thing to note here is that this is more granuality and sharing can be facilitated if need be.
The unified shading architecture will likely differ a fair bit from Cell. Cell will approach matters in running software to deal with the way software will run on the machine. While the graphics architectures will use hardware to run the software on the machine. Of course, there will eventually be microcode programming et al and finally the two approaches will converge.
But the level of abstraction that Josiah is talking about is definately less abstract and his points remain quite valid. I have yet to see a good argument to the contrary.
Saem said:
That is my point, and this:
Begs the question of how you can draw such a distinction when developers can already do rudimentary physics in shaders I believe and if not will be able to soon enough.
There is no fundimental micro-architectural difference between a VU, an APU, or a future VS/FS. Hell, I just read in another thread about a guy who networked like 30 workstation NV3x's and ran weather simulations on them.
In both cases there is an underlying hardware which has software running on/over it. In both cases, especially in a Unified Shading Architecture and Cell, you'll see developer input changing the allocation of resources to some extent - if this is consciously manipulated via the Cell software developer or a driver-esque automatic compiling/allocating is irrelevent. Perhaps you can draw a line in this grey, I don't personally as I see where it's going.
Obviously I disagree. And I'll respond to him when I get back, but I need to run out.
nondescript
Regular
It's been 12-hours since I last checked the thread...so some of this is going to be about things 20 posts ago.
To whoever posted the Micron stuff:
Yeah, that sounds very promising. Micron's starting from the memory end and building logic, while Clearspeed starting from the logic end and is embedding more memory close to the processors. Definitely, I think the ultimate solution is somewhere in between, with logic and memory units close together, and ridiculous amounts of bandwidth.
Like Hannibal (the Arstechnica guy, not the Carthaginian general) said, the bottleneck for PCs is definitely the bus speed and latency - putting memory w/ logic solves this problem. Which is why eDRAM is so important for CELL.
Cell like FPGA?
I don't pretend to know what CELL is, other than what I can scrounge from the patents and from other ppl who have, but its definitely not a FPGA.
I've used the Xilinx Spartan line of FPGAs, and all it is 5000 or so "slices" of logic and memory. Each slice has some flip-flops, and a two-tier AND-OR array for combinatory logic. There are another 200 or so I/O modules that you can assign the chip pins to. You design a circuit, the Xilinx complier maps it on to the chip, and you have your circuit. You can't reprogram the hardware on the fly, you need to restart each time you change the logic. "Field-Programmable" simply means it doesn't take special equipment to reprogram it.
FPGA don't "optimise themselves to a certain task by effectively allocating it's processing elements via software for whatever tasks are thrown at it." (Saem) They don't do anything at all unless you design it in.
An FPGA is a bunch of components. You build things with the components. Sure, you could build a CELL-like chip with an FPGA - but that's your design and not an intrinsic property of the FPGA itself.
FPGA's are used for prototyping and low-volume applications where it isn't economical to fab a ASIC.
That's very different from CELL.
To whoever posted the Micron stuff:
Yeah, that sounds very promising. Micron's starting from the memory end and building logic, while Clearspeed starting from the logic end and is embedding more memory close to the processors. Definitely, I think the ultimate solution is somewhere in between, with logic and memory units close together, and ridiculous amounts of bandwidth.
Like Hannibal (the Arstechnica guy, not the Carthaginian general) said, the bottleneck for PCs is definitely the bus speed and latency - putting memory w/ logic solves this problem. Which is why eDRAM is so important for CELL.
Cell like FPGA?
I don't pretend to know what CELL is, other than what I can scrounge from the patents and from other ppl who have, but its definitely not a FPGA.
I've used the Xilinx Spartan line of FPGAs, and all it is 5000 or so "slices" of logic and memory. Each slice has some flip-flops, and a two-tier AND-OR array for combinatory logic. There are another 200 or so I/O modules that you can assign the chip pins to. You design a circuit, the Xilinx complier maps it on to the chip, and you have your circuit. You can't reprogram the hardware on the fly, you need to restart each time you change the logic. "Field-Programmable" simply means it doesn't take special equipment to reprogram it.
FPGA don't "optimise themselves to a certain task by effectively allocating it's processing elements via software for whatever tasks are thrown at it." (Saem) They don't do anything at all unless you design it in.
An FPGA is a bunch of components. You build things with the components. Sure, you could build a CELL-like chip with an FPGA - but that's your design and not an intrinsic property of the FPGA itself.
FPGA's are used for prototyping and low-volume applications where it isn't economical to fab a ASIC.
That's very different from CELL.
nondescript
Regular
nondescript said:
Getting back to it.
First, the 1.0V:
Looking and the SIA roadmap for high-performance chips, we see that the projected voltage for the 100nm node is 1.2-0.9V, for the 70nm node is 0.9-0.6V and for the 50nm node is 0.6-0.5V. The SIA doesn't expect 70nm to be attained until 2008, and 50nm until 2011 - but STI is a little ahead of the curb here. If CELL is being fabbed at 65nm, 1.0V is already a conservative estimate.
SIA Roadmap: http://public.itrs.net/files/1999_SIA_Roadmap/ORTC.pdf
Page 18 for the power projections.
Now, for the blanket 20% power savings.
With SOI and eDRAM and all that good stuff, we can expect power savings beyond the simple scaling of bulk CMOS.
http://pr.fujitsu.com/en/news/2001/02/9-1.html
http://www.ssec.honeywell.com/aerospace/new/080699.html
As you can see, 20% is already a conservative estimate.
So there, that's my justification.
Re: ...
Ok, read what you just wrote. To me the difference between Cell running a shader program on an arbirary number of APUs is just about equivalent to a NV50 or R500 running a Shader program on a Unified Shading Architecture with an arbitrary number of constructs running it. Under both are clusters of FP logic which is being controlled per application and churning out data. In both circumstances there are finergrained constructs which are arbitrarily divided on a per task basis, which I'll touch on after the following reply.
Ok, this is true but not going anywhere.
Who ever said this? The patent outlined hardwired functionality for the "dumb" raster functions which are highly iterative (eg. Filtering, etal). It's just that in front of these pseudo-pipelines are a significant amount of FP logic that's arranged in constructs composed of 4 FPUs and 4 FXUs. As opposed to the R300's VS which has something like a 4-way SIMD unit and scalar pipe, which is almost the same, no? Perhaps closer to a VU than an APU. Correct me if I'm wrong, I think I might be because I think the R300's are more complex, like multi-tiered - regardless, the idea remains constant.
And application is irrelevent, but just to throw it in. You can already do some level of scientific apps "in software" as you like to say on a Graphics card. This will only get more common with time.
Josiah said:
Ok, read what you just wrote. To me the difference between Cell running a shader program on an arbirary number of APUs is just about equivalent to a NV50 or R500 running a Shader program on a Unified Shading Architecture with an arbitrary number of constructs running it. Under both are clusters of FP logic which is being controlled per application and churning out data. In both circumstances there are finergrained constructs which are arbitrarily divided on a per task basis, which I'll touch on after the following reply.
Vince said:
Ok, this is true but not going anywhere.
Who ever said this? The patent outlined hardwired functionality for the "dumb" raster functions which are highly iterative (eg. Filtering, etal). It's just that in front of these pseudo-pipelines are a significant amount of FP logic that's arranged in constructs composed of 4 FPUs and 4 FXUs. As opposed to the R300's VS which has something like a 4-way SIMD unit and scalar pipe, which is almost the same, no? Perhaps closer to a VU than an APU. Correct me if I'm wrong, I think I might be because I think the R300's are more complex, like multi-tiered - regardless, the idea remains constant.
And application is irrelevent, but just to throw it in. You can already do some level of scientific apps "in software" as you like to say on a Graphics card. This will only get more common with time.
Vince,
Stupid issues with articulating arguments on the net.
So my take on the matter is Josiah's PoV is valid and isn't all wrong. Now that doesn't mean I think yours (Vince) is wrong. One of the points of my post was to elaborate on the grey area and then draw a line in it to define what your side and Josiah's side are.
Additionally, note that I mentioned that they're convergent paths! I don't think Josiah's arguement as I understand it excludes this possiblity. I think you're arguing your (Vince) position too strongly.
Stupid issues with articulating arguments on the net.
So my take on the matter is Josiah's PoV is valid and isn't all wrong. Now that doesn't mean I think yours (Vince) is wrong. One of the points of my post was to elaborate on the grey area and then draw a line in it to define what your side and Josiah's side are.
Additionally, note that I mentioned that they're convergent paths! I don't think Josiah's arguement as I understand it excludes this possiblity. I think you're arguing your (Vince) position too strongly.
DeadmeatGA
Banned
....
From the ClearSpeed product pdf..
From the ClearSpeed product pdf..
See? PixelFusion doesn't do auto parallelization out of serial code.
nondescript said:
The idea for combining DRAM and Logic has been around for awhile. It is mainly refered to a IRAM (Intelligent RAM). It looks like Micron is calling their version of it Active Memory.
One of the people thats the driving force behind IRAM is Dave Patterson. His research credits include the RISC CPU design standard and the RAID standard that many file servers utilize. Dave Patterson is a real heavy weight when it comes to research. So after RISC and RAID his third big project is the IRAM concept.
Here is a good article from Wired August of 1996.
http://iram.cs.berkeley.edu/articles/wired.85.lo.jpg
Another fun to read article on IRAM.
http://iram.cs.berkeley.edu/papers/IRAM.computer.pdf
Anyway, could the rumor that Team X-Box reported on that Microsoft has signed a contract with IBM be for an IRAM chip for the X-Box 2?
http://www.cs.berkeley.edu/~pattrsn/articles/RedHerring.html
This is a good article also.
http://www.coe.berkeley.edu/labnotes/0102iram.html
DeadmeatGA
Banned
...
Well, I got the die size data of CS301.
Sorry, Kutaragi's dream of 1 TFLOPS per chip still has to wait until 2007 or 2008 and still cost a bucketload of cash to afford....
Well, I got the die size data of CS301.
For CELL fans, don't cheer yet because CS301 is a SIMD processor; only one instruction decoder, one control unit and one instruction cache shared among 64 FPUs, and is not heavily pipelined to support higher clock. EE3 on the other hand is a 18-way MIMD(2 PPC cores + 16 active VUs + 2 spare VUs) plus 2 MB of SRAM cache, so it will no doubt be massive in dize size and give a poor yield, plus a programming model that makes CS301 programming look like a kiddy stuff.
Sorry, Kutaragi's dream of 1 TFLOPS per chip still has to wait until 2007 or 2008 and still cost a bucketload of cash to afford....
Megadrive1988
Veteran
Deadmeat, do you feel that PS3 will offer the same leap over PS2, as PS2 offered over PS1?
I know you are not a fan of PSX/PS1 or PSX2/PS2, and I am not either.
Sony has not yet showed they are capable of impressive graphics quality. sure their Playstations were very powerful opon their releases
(lots of polygons for the time) oh, and they did have the first consumer device with embedded memory (Graphics Synth in PS2) but that's about it.
I am more of a fan of Lockheed Martin's Real3D, PowerVR and ArtX/ATI.
(but wait Sony fans!)
I do however have some hope that PS3 will offer much improved graphics quality and new way of rendering real-time graphics. I dont know if PS3 will reach 1TFLOP or not. It doesnt really matter if its 900 GFLOPs or 1.2 TFLOPs, PS3 will only get 100~300 sustained GFLOPs anyway. what *will* matter more, is if developers can do something new, with any given amount of flops. new way of rendering (procedural textures, dynamic lighting, sub-division, shaders etc.)
And I'm also looking forward to PSP for the simple fact that it will FINALLY bring true competition to the handheld arena, thus cooler games.
I know you are not a fan of PSX/PS1 or PSX2/PS2, and I am not either.
Sony has not yet showed they are capable of impressive graphics quality. sure their Playstations were very powerful opon their releases
(lots of polygons for the time) oh, and they did have the first consumer device with embedded memory (Graphics Synth in PS2) but that's about it.
I am more of a fan of Lockheed Martin's Real3D, PowerVR and ArtX/ATI.
(but wait Sony fans!)
I do however have some hope that PS3 will offer much improved graphics quality and new way of rendering real-time graphics. I dont know if PS3 will reach 1TFLOP or not. It doesnt really matter if its 900 GFLOPs or 1.2 TFLOPs, PS3 will only get 100~300 sustained GFLOPs anyway. what *will* matter more, is if developers can do something new, with any given amount of flops. new way of rendering (procedural textures, dynamic lighting, sub-division, shaders etc.)
And I'm also looking forward to PSP for the simple fact that it will FINALLY bring true competition to the handheld arena, thus cooler games.
TheMightyPuck
Newcomer
I still think the bottleneck in next generation consoles is going to be developer talent (of course I guess that is always the case). Sony's biggest challenge ain't CELL. It isn't even exectuting on cost effective console hardware (over the course of its life including any die shrinks, integration of components etc.) It is providing development tools for the CELL based PS3 to make possible reasonable production times and costs for PS3 games relative to the competition. Of course in the existing Sony dominated marketplace, non AAA developers are willing to invest more time and money into developing PS2 software than they would for other platorms. If PS3 is a cheap and easy box to develop for, it will be able to leverage its massive brand advantage into continued console dominance even if its hardware doesn't quite live up to the hype.
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