CELL technology afterthought? (also rate it's technology...)
- Thread starter Josh378
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Even better vid of the presentation I gave it a 9. I'm reserving the 10 for quantum or optical computers.
For some time now, we reached a point in computing where there's no way of increasing speed if not through parallel processing and increased memory access/bandwidth.
I think CELL represents the first mainstream effort in an all-out parallel computing system. Like it was in the transition between structured programming and OOP, programmers will have to adapt to this new way of coding. And IMO, CELL might just be later known as the father of a new standard of programming. Just a feeling.
For some time now, we reached a point in computing where there's no way of increasing speed if not through parallel processing and increased memory access/bandwidth.
I think CELL represents the first mainstream effort in an all-out parallel computing system. Like it was in the transition between structured programming and OOP, programmers will have to adapt to this new way of coding. And IMO, CELL might just be later known as the father of a new standard of programming. Just a feeling.
Theres not much revealed yet, just theorectical performance numbers. I`d like to see how you actually keep all SPUs equally busy, whats this "OS-neutral" (stooopid Buzzword) Talk is about, and so on.
It will be a beast however and I hope it will make a real Dent in the x86 Market, but I was already hoping that yesterday
It will be a beast however and I hope it will make a real Dent in the x86 Market, but I was already hoping that yesterday
They haven't really revealed dick so far about the chip, only embellished marginally on some of the things we already knew about the damn thing, such as cache/memory pool sizes etc.
I've yet to see anything concrete about specific facts about the powerpc core for example, about the internal bus structure, signalling rate for the XDR memory interfaces, tons of stuff.
I've yet to see anything concrete about specific facts about the powerpc core for example, about the internal bus structure, signalling rate for the XDR memory interfaces, tons of stuff.
No rates, but some significant points.
- 256KB per SPU, higher than the 128KB expected, lightyears ahead of VU1 32KB and VU0 16KB. I can almost hear devs weeping in relief.
- 512KB L2. Also galaxies beyond EE MIPS 32KB. More devs weeping.
- Impressive mem bandwidth confirmed, and we know that is a key performance attribute. As important, or even more important than flop numbers.
- They showed a real chip.
BUT
- GPU part still unknown.
- Programming model still not clear.
- C/C++ compiler for SPU mentioned, but how good?
- 256KB per SPU, higher than the 128KB expected, lightyears ahead of VU1 32KB and VU0 16KB. I can almost hear devs weeping in relief.
- 512KB L2. Also galaxies beyond EE MIPS 32KB. More devs weeping.
- Impressive mem bandwidth confirmed, and we know that is a key performance attribute. As important, or even more important than flop numbers.
- They showed a real chip.
BUT
- GPU part still unknown.
- Programming model still not clear.
- C/C++ compiler for SPU mentioned, but how good?
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