arjan de lumens
Veteran
I would like to point out that there are a bunch of misconceptions floating around here about the VIA C3:
- Early C3's ('Samuel' and 'Ezra') didn't have CMOV; later C3's based on the 'Nehemiah' core do have it, though.
- The branch predictor of the C3 processors is actually quite sophisticated, using a gshare+agree predictor which reaches about the same prediction rates as the predictors in, say, an AthlonXP processor.
- Despite it being called 'Cyrix III' for a while, it is NOT based on any architecture that Cyrix ever developed - instead it is based on a desgn by Centaur, which was bought up by VIA around the same time as Cyrix was.
- The FPU it has is non-pipelined and in some models run at 1/2 clcok speed.
- It has only 1 integer ALU (whereas e.g. the Athlon has 3)
- It is in-order, so that it cannot reorder/schedule instructions across jumps or L1 cache msses or potentially-exception-generating instructions or high-latency instructions the way OOO processors can.