ATI & XBox

Paul,
I know you must feel that the “Engineâ€￾ speaks for itself.
But in order to avoid the pitfalls of just assuming, I remain apart.
A link or quote would be very helpful.
And hopefully remove doubts that it is a Server Processor for PS2 & PS3 gaming.

I have searched to my limits finding this.
http://library.consusgroup.com/library_pvw/147/147201.asp
But $56 is more that I care to spend on this curiosity.

WHEREAS, the parties desire to cooperate with each other to enable SCE
and Toshiba (and [*] as SCE's sublicensee) to implement Rambus' Redwood Rambus
Interface Technology and Yellowstone Rambus Interface Technology as the bus
interfaces in and with the Broadband Engine (and related [*] designed to [*] to
the [*] on the terms and conditions set forth herein

It says Yellowstone and Redwood ‘in’ a broadband engine.
I believe you could use it in an MCM. But could you use it in a processor?

So please understand my position or quandry.
As 1 PE and 1 VS make more sense to me.
 
I have the full document.

Broadband Engine is, and has always been, the Celluar based MPU for use in the Playstation 3 game console.

Developed by Toshiba and SCE using the Cell architecture and IBM tech(SOI, Low-k) the Broadband Engine will use Rambus Redwood as the bus interface(think going from BE to VS) and XDR DRAM(PS3 main DRAM, DUH!).

It was already confirmed that Toshiba and SCE liscensed XDR(at that time Yellowstone), and Redwood for use in PS3.

This is the contract of that agreement, it states the specific embodiment of Cell, the Broadband Engine to be used in PS3.

I have the document, to paste things from it that are not free would be illegal and I'm not doing it.

At anyrate it doesn't matter, it's you vs everyone here.
 
I believe you could use it in an MCM. But could you use it in a processor?

Redwood is only needed when you go offchip. It's a chip to chip interface and compared to onchip it's relatively slow. Redwood is analogous to HyperTransport.
 
Paul said:
At anyrate it doesn't matter, it's you vs everyone here.

That's a strong statement.

To be honest I would be overjoyed to learn this to be a fact.
I believe you and your conviction.

But would you entertain some questions?

Such as is the PU ~ PPC440 or MIPS64 20Kc based?
How much XDR memory bandwidth does it mention? (anything like Bits, frequency, channels, etc?)

PC Engine, Thank you.
(I typed that to make a point and express my doubts.)
 
To be honest I would be overjoyed to learn this to be a fact.

I'm not out to try and prove that the Broadband Engine used in PS3 will be the 4Ghz 1TFLOPS and 1TOPS monster from the patent, it could just be a single PE yielding 256GFLOPS(Though STI would have failed in their goal). I am just trying to say that the PS3 Cell based CPU is the Broadband Engine, which it is.

Such as is the PU ~ PPC440 or MIPS64 20Kc based?
How much XDR memory bandwidth does it mention? (anything like Bits, frequency, channels, etc?)

There is alot more legal shit in it than answers, such details on the XDR memory are blanked out. However the rest is really good.
 
David_South#1 said:
But I had no idea that SSX3 & Balder’s Gate used full frame buffers.

Baldur's Gate: Dark Alliance engine use a half height front buffer (but it's Back buffer is supersampled 4x (1280x iirc)). :D

Sure, it could have been in full frame but they would have to forget about the ssaa.
 
David_South#1 said:
I am unable to perceive 32 pair of VU0&VU1 on a single chip with 4 PU (Whether it be PPC440 or MIPS64 20Kc), and 4 DMACs.

Hm, there are no VU0/1 in the Cell architecture. The sub-processors are called APUs and they're not analogous to the VUs in PS2, though they share similarities. There's 8 APUs per processing element. The PU is PPC-based, not MIPS-based. This was announced ages ago, though nobody outside the involved parties know what flavor of PPC. Probably nothing too fancy, since the PU doesn't deal with the grunt of the workload anyway.

At no time have I or am I going to suggest an MCM in a console.

Fair enough, it seemed to me like you did, but I'll take your word for it. Anyway, a MCM would go against the idea of Cell, with the BB chip as a central repository of memory, computing power and bandwidth.

It is because I believe Broadband Engine to be an MCM that I stand against suggestion of its use in a console.

Well, the BB chip WILL be what powers PS3. Hopefully it will be the "preferred" incarnation described in the patent with 4 PEs and 64MB eDRAM, but who knows. Time will tell...

To support SCE’s Final Fantasy Movie Demos, they used an SGI Origin 3000.

The Origin server line isn't particulary powerful these days, and Origins from several years ago are even less so. Anyway, it was the GSCube which did all the rendering for the demo, the server was just mass storage and for controlling the show (AFAIK, the GSCube lacks mouse/keyboard input for example).

For SCEI, the SGI Origin 3000 series represents "the kind of power needed to fuel the next generation of broadband entertainment," said Ken Kutaragi
Do ya’ll really think something like that will be used in a console?

Though the quote is dated now and SGI might not be a part of the cell vision anymore, what he speaks of is almost without a doubt using these Origins across the internet as downloadable content servers or game-host servers. I'm sure he doesn't mean everybody needs a rack cabinet in each of our homes! ;)
 
Guden Oden said:
Hm, there are no VU0/1 in the Cell architecture. The sub-processors are called APUs and they're not analogous to the VUs in PS2, though they share similarities. There's 8 APUs per processing element. The PU is PPC-based, not MIPS-based. This was announced ages ago, though nobody outside the involved parties know what flavor of PPC. Probably nothing too fancy, since the PU doesn't deal with the grunt of the workload anyway.

I know that they are called APU. But to demonstrate why I find the scale of a BE so hard to accept, I'm using familiar terms and ideas. The way APU are reduced in size to VU is made up for by the amount of memory and local bussing in each one. So it's my feeling that their dye scale is somewhat alike.

PPC as PU. This makes good sense. Cell is an IBM product and has been referred to as an extension of the Power family. MIPS and IBM both produce RISC cores. So IBM Power could replace MIPS. But I have records of SONY and Toshiba licensing MIPS64 and developing it to at least the expected 1GHz needed of a PU. While people I respect like Panajev have told me this was announced...I didn't get the memo.
Please forward the memo to me. (Link and/or quote)

DS: It is because I believe Broadband Engine to be an MCM that I stand against suggestion of its use in a console.

GO: Well, the BB chip WILL be what powers PS3. Hopefully it will be the "preferred" incarnation described in the patent with 4 PEs and 64MB eDRAM, but who knows. Time will tell...

This isn't the first time someone has suggested 64MB of eDRAM.
Please show me where ya'll are getting this idea. The patents as I've read suggest that 64MB is the preferred amount for each Sony Element. But that it is off chip. The VS has an image cache/eDRAM on chip. But the VS patents describe it as 32MB, not 64. (Please quote the patent # you got this figure from.)

The Origin server line isn't particularly powerful these days, and Origins from several years ago are even less so. Anyway, it was the GSCube which did all the rendering for the demo, the server was just mass storage and for controlling the show.

Though the quote is dated now and SGI might not be a part of the cell vision anymore, what he speaks of is almost without a doubt using these Origins across the internet as downloadable content servers or game-host servers. I'm sure he doesn't mean everybody needs a rack cabinet in each of our homes! ;)

I know what Origin did and what GScube was created to do, research tiled-rendering.
I know that SGI is not part of Cell or Playstation3, but that it's modular NUMAflex architecture is (in some ways) imitated by Cell.
Even though this machine is out of date, it represents what Sony is working to produce.

My point is that the GScube is representary of a VS Engine (4x VS). [/b]
The Origin 3000 is representary of the BroadBand Engine (4x PE).

When given this example you came to the same conclusion that I did.
That such a device would not be in the home. It would be a server that distributes downloadable content (Video on Demand) and/or functions as an online game-host.

David South
 
Please show me where ya'll are getting this idea. The patents as I've read suggest that 64MB is the prefered amount for each Sony Element. But that it is off chip

You don't put external DRAM on such a ridiculously fast bus(1024bit).

That such a device would not be in the home. It would be a server that distributes downloadable content (Video on Demand) and/or functions as an online game-host.

Said device will power the Playstation 3, better get used to the idea.
 
Paul said:
You don't put external DRAM on such a ridiculously fast bus(1024bit).

Where can you show me that 64MB would be on a 1024 bit buss?

Visit granted patent 6,526,491.
http://patft.uspto.gov/netacgi/nph-....WKU.&OS=PN/6,526,491&RS=PN/6,526,491

"a server may employ four PEs, a workstation may employ two PEs"

"PE 201 is closely associated with a dynamic random access memory (DRAM) 225 through a high bandwidth memory connection 227. DRAM 225 functions as the main memory for PE 201."

Please look at figures 2 and 3.
Bussed 227 and 313 are not on the processor.
If you have proof that they are please share.

And there aren't any details beyond "high/broad bandwidth connection".
Note it says, "connection" and not "buss".

If you know of any place that says 1,024bit connection, please share.
But so far as I understand this memory is 64MB, and is likely XDR DRAM.

Also, Please consider how big 64MB of eDRAM would be.
Are you honestly able to picture it built into a chip that has 8 APU?
Embedded DRAM alone would be nearly the size of EE+GS @ 90nm.


Silent note, ignore ~
Figures either 8 or 9 are what I believe will become PS3.
Figure 8 if they can only fit 4 APU on a chip, 9 if they can fit 8APU.
 
We covered all this and came to an agreement over a year ago, that 64mb of DRAM is embedded, whether the final Broadband Engine will feature a full 64mb of e-DRAM is up for debate; but they are talking about e-DRAM.

The fact that they are talking about a 1024bit bus is mentioned several times in the patent, your just not looking hard enough.

Also, Please consider how big 64MB of eDRAM would be.

You didn't read Vince's latest masterpiece, did you?

Figures either 8 or 9 are what I believe will become PS3.

That's not what Sony has planned, sorry! Of course they may not hit their goals, but you can rest assured they are aiming and trying to build a Teraflops monster.
 
They mention the 1024bit switched buss many times.
Especially about the DMAC.
But not once is it the connection used by the DMAC to the DRAM.

Please show me a quote from it that says otherwise.


Yes, they are aiming to build a Teraflop processor...

...by the 2010.

Until then it is my belief that it will take multiple chips to achieve that goal.
 
You don't put external memory on a huge fast bus if you don't have enough memory to store everything needed by the system. It's silly, this is simple stuff David. :D

I'm done arguing, we all can think whatever we want to think, we'll see what happens later this year.

As for your 2010 comment about STI, let's just say this is not accurate. Oh I don't know.. Call it Intuition ;)
 
Im thinking Cmos Static ram. The speeds are higher then Dram and the new Cmos static is much cooler running and uses less power then the older Nmos Static.
 
Paul said:
You don't put external memory on a huge fast bus if you don't have enough memory to store everything needed by the system. It's silly, this is simple stuff David. :D


You said my view is silly. :?
Check out the new IBM patent thread.
Because it looks like IBM is just as silly. :p


Sincerely though,
I would like to know where you got the 1024bit buss to 64MB eDRAM from?
 
{Sniping}Waste said:
the new Cmos static is much cooler running and uses less power then the older Nmos Static.

New? :LOL:

We've been running on CMOS since like the late 80s or something like that man... Nobody's used NMOS for anything for ages. :)
 
Guden Oden said:
{Sniping}Waste said:
the new Cmos static is much cooler running and uses less power then the older Nmos Static.

New? :LOL:

We've been running on CMOS since like the late 80s or something like that man... Nobody's used NMOS for anything for ages. :)

There is a newer CMOS static out now. Its about a year old now. It only powers up in write and reads. This lower the heat big time and the power usage.
 
Yes, they are aiming to build a Teraflop processor...

...by the 2010.

well, Sony execs have been quoted saying Cell processors would have teraflops of processing power. I think 1 TFLOP is *possible* by 2006 and TFLOPS by 2010. we shall see.
 
...

It's amazing some SCEI fans still have hopes for the teraflop CELL, when the patent documents makes it clear they are talking about a single PE / single rasterizer device....
 
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