Bouncing Zabaglione Bros.
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Good grief, can you smell the desperation? They can't move forwards, so they are moving backwards. 
AMD's culture clash
- Thread starter John Reynolds
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Good grief, can you smell the desperation? They can't move forwards, so they are moving backwards.
It may be worse, going by the preliminary results from Tech Report.
http://www.techreport.com/articles.x/13741
After taking into account the TLB patch needed until the B3 stepping (1Q 08?), and the fact that the engineering samples AMD used for the reviews pegged the northbridge clocks too high, moving backwards is in some cases a performance improvement.
The northbridge clock shenanigans are really shady.
Well, at least we know where Phenom will be in a few months:
exactly where they pretended to be a month ago, which will be an improvement.
Phenons and Barcelonas at 3GHz?
Sure, at 200W TDP. January's kindof cold, so that could be a bonus...a new tech, AMD Warm&FuzzyTM
. Seriously now, I'm not holding my breath for those coming anytime soon(read, in a few months). I'd love to be proven wrong though, although that would annoy me to no end considering my Maximus is on the way and I'm trying to snatch a 9650 or 9770(which is hard when you live in the wild wild east of europe).
Is this actually confirmed(as in reliable source stating it, even if behind closed doors). You can get 9650s relatively easily...
It would be a first if any non-trivial chip put out by any manufacturer didn't have a bug.
AMD and Intel document errata for their chips, and other manufacturers that don't have such lists available simply neglect to mention them publically.
What bug exactly are you talking about?
They're not bugs, they're "errata"...I've been edumacated on the subject. 
I'd assume this one:
http://www.techreport.com/discussions.x/13756
"45nm Core 2 Quad launch delayed due to erratum?"
If there is an erratum that only affects the quad-cores, that points to a problem or race condition dealing with shared state or traffic over the FSB.
Penryn adds cache capacity, but that shouldn't matter too much.
The FSB may be a little faster, but Intel would probably postpone the initial bus clock increase rather than delay the launch.
Intel does claim Penryn improves virtualization performance, which is a ripe area for such bugs. Virtualization is apparently the big area where K10 suffers from its TLB bug most often.
If it's not the new virtualization stuff, I'm curious as to whether this new testing method would find a similar problem with current Core2 quads.
Penryn adds cache capacity, but that shouldn't matter too much.
The FSB may be a little faster, but Intel would probably postpone the initial bus clock increase rather than delay the launch.
Intel does claim Penryn improves virtualization performance, which is a ripe area for such bugs. Virtualization is apparently the big area where K10 suffers from its TLB bug most often.
If it's not the new virtualization stuff, I'm curious as to whether this new testing method would find a similar problem with current Core2 quads.
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