AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Discussion in 'Architecture and Products' started by ToTTenTranz, Sep 20, 2016.

  1. Kaotik

    Kaotik Drunk Member
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    You'd need 3 chips / 96-bit membus with GDDR5X to reach over 100 GB/s
    Would it really be notably cheaper than sticking one 4-Hi HBM2-stack there, which would offer over twice the bandwidth to boot?
     
  2. ToTTenTranz

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    What about a single HBM1 stack? If SK Hynix is still making them and Fiji is to be replaced with Vega on all fronts, those single stacks could be cheap enough by now.
     
  3. Alexko

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    Yeah but two 14Gbps GDDR6 chips would provide 112GB/s, which is well over twice the bandwidth provided by a dual-channel DDR4-3200 setup. It's hard to estimate the cost but my guess would be that this would be cheaper than a stack of HBM2. I doubt there's any point in using HBM1 at this point, the low volumes probably make it unattractive from a cost perspective.
     
  4. Anarchist4000

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    I'd even question if a 2-Hi stack was an option. Should still offer full bandwidth, but cheaper and more than sufficient for low end boxes. However 8-Hi might be "cheaper" if it allows doing away with system memory.

    Possibly, but the benefits of more bandwidth for an APU may be worth the trade-off at the bottom of the market. Higher up, HBM superior in capacity and both of those configurations would be interchangeable.
     
  5. Alexko

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    You know, on second thought
    • Vega 10 has about 13000 GFLOPS and 480GB/s; that's about 27 FLOP/B,
    • Raven Ridge (11 CUs, maybe 1GHz) should have about 1400 GFLOPS and perhaps 51.2GB/s (DDR4-3200); that's about 27 FLOB/B too.
    So it might not be in such dire need of more bandwidth after all.
     
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  6. Anarchist4000

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    Vega10 also has 45MB of SRAM that probably reduce that need a bit as cache size doesn't scale. Also need to consider the CPU still has its own work and there could be bandwidth intensive applications that would benefit. Power would be another consideration as HBM would use less energy than DDR4. It's not a bad idea, but HBM would have been designed for this usage.
     
  7. ToTTenTranz

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    If it's the same architecture, I doubt the iGPU in Raven Ridge will clock only at 1GHz. I think 1.15 to1.2GHz is a more believable baseline.

    Except of course for the lower power mobile versions, in which case the APU won't be using DDR4 3200 anyways.
     
  8. Arnold Beckenbauer

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  9. DavidGraham

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  10. Scott_Arm

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  11. Rootax

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    I guess so yes. It's a pretty sad result considering the delay, power usage&co, but, they have no choice to release that I guess. I hope some Vega tech will be used in Navi, otherwise it would be such a waste.
     
  12. Cat Merc

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    Mind you, both of those are DPM7 clocks of Air and Water respectively. We don't know if it's actually sustaining it.

    Anyway, I went ahead and looked at the score split:
    1080 Ti is 17% faster in graphics test 1, and 33% faster in graphics test 2

    From 3DMark technical guide:
    [​IMG]

    Speculate as you will.
     
  13. w0lfram

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    I have a simple question.
    When discussing "bandwidth", what components within a GPU, does bandwidth matter back & forth ? At such bit depth.

    Memory?
     
  14. Rasterizer

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    Well, seeing as an air cooled Vega FE scored 7,126 on June 28 using driver 22.19.384.2, my inclination is to suspect old drivers because the alternative would require believing that enabling AVFS and DSBR in RX Vega's drivers is worth exactly ~0%, and that nothing has been achieved in terms of correcting the memory bandwidth issues on Vega FE, but that would seem to be incompatible with the ETH hashrate rumours.
     
  15. DavidGraham

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    Yes Indeed.
    As previously stated by AMD to PCPer and GamersNexus, Vega FE driver already has all the gaming optimizations until it's release. So RX driver could've really had almost nothing new to add to the table in that regard.
    AMD already implied not to expect great differences due to the activation of DSBR.
    Who said memory bandwidth needed a driver to be corrected?
     
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  16. pharma

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    So basically no FP64 on the Instinct MI25 accelerators?

    https://www.top500.org/news/amd-demos-petaflop-in-a-rack-supercomputer/
     
  17. Cat Merc

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  18. AlexV

    AlexV Heteroscedasticitate
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  19. ToTTenTranz

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  20. 3dilettante

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    I think the specifically cited instruction was the XAD_U32 instruction, which the document indicates is meant to accelerate SHA256 hashing.
     
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