AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Discussion in 'Architecture and Products' started by ToTTenTranz, Sep 20, 2016.

  1. silent_guy

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    BW limited or not, a 1080 has a BW of 256GB/s. Vega has almost double that. The lack of DSBR is not a sufficient explanation.
     
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  2. CarstenS

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    Strange that Resource Binding ist listed for Pascal still as Tier 2. Recent drivers showed it to be Tier 3. And the Vega FE driver at least did not yet support Standard Swizzle - good to see it's finally getting picked up by someone!
     
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  3. sebbbi

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    Radeon GPU profiler doesn't have bandwidth graphs yet. I have requested this feature (along other bottleneck graphs). This tool has proven already to be a huge improvement for understanding AMD PC GPUs and drivers at low level. When we eventually get bandwidth graph support, I can analyze some Vega captures. Don't expect this to happen at RX launch however.
     
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  4. Ryan Smith

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    It's possible, but I'm going to guess not. From the tone of the conversations I had, while DSBR will improve things, everyone was quick to point out that the gains would be higher on a more resource-constrained card. Those aren't the kind of comments I'd expect if they thought performance would make a huge jump with DSBR.

    [​IMG]
     
    #3184 Ryan Smith, Jul 31, 2017
    Last edited: Jul 31, 2017
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  5. sebbbi

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    Pascal has very good tiled rasterizer, very good DCC and a large L2 cache. Benchmarks have proven Pascal DCC to be significantly ahead of Polaris (GCN4). Vega FE current drivers have disabled tiled rasterizer. Because of all these advantages, Pascal can get away with 256 GB/s. And obviously these bandwidth saving mechanisms also save significant amount of power.
     
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  6. 3dilettante

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    It's been AMD's track record for ages, and it has the track record of competitive success to match.
    It's helpful to improve over time if one starts in a leading or competitive position, and it's something of a double-edged sword with the following:

    To note, the quoted review was a nearly 1-year later retrospective, and that was for an easier transition.
    I don't mind seeing things dissected a long while after the fact, but having a multiplier applied to the a year's worth of incremental improvement will leave me struggling to be interested.

    Perhaps if they ever open up as to why, it might be interesting. It's pointing to a potentially fragile or flawed feature, which means perhaps waiting for version 2.0 or perhaps someone else who has a somewhat similar tech going to an even higher version number.
     
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  7. sebbbi

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    I am glad for standard swizzle too, but we need also Nvidia support to make it a relevant feature. Pascal was upgraded to binding Tier 3 a few days ago. Most likely these slides were made before that.
     
  8. 3dilettante

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    AMD's patents put the emphasis of a binning deferred rasterizer on the avoidance of pixel shader work in the presence of overdraw. The choice to measure DSBR in terms of bandwidth saved doesn't directly measure that impact, which may align with statements that it matters more for resource-constrained cards.
    One potential wrinkle among many is that a decent chunk of the pipeline is dependent on wave packing, pixel quads, ROP tiles, or cache lines as the granularity, and the DSBR in complex scenarios would be prone to spitting out fragments that would wind up taking up resources or data movement at those levels regardless. The rumors of SIMD-length changes or better packing seem to be a "wait for gen N+1" at this point.
     
  9. sebbbi

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    Software engineering has grown to be a huge part of any hardware launch. I would guess that this feature requires lots of driver code (some running on CPU, some on command processors). You can ship a fully functional hardware without good software support. Obviously this is not ideal situation for marketing, since people tend to judge products at launch date. But at least they now have a tiled rasterizer that they can improve upon (whether software or hardware changes or both).
     
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  10. BacBeyond

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    http://techreport.com/review/31224/the-curtain-comes-up-on-amd-vega-architecture/3

    Hmm yeah, doubt we'll see any performance and better power usage once that is enabled...
     
  11. CarstenS

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    In their footnotes, they cite the 384.76 drivers being used for performance comparisons, which also enable Tier 3 RB.
     
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  12. BacBeyond

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    Did anyone confirm that they do support Tier 3 and that it wasn't just the driver reporting incorrectly?
     
  13. CarstenS

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    So, judging from our Spec ViewPerf Results in energy-01, where we got 20,4 mean score, DSBR indeed WAS enabled on Vega Frontier edition for this particular workload at least.
     
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  14. CarstenS

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    That being a WHQL driver, I'd try to get a refund on the fees paid to microsoft for certification if such a big mistake slipped past. :D
     
  15. DavidGraham

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    Sorry, that's just grasping at straws, AMD has the data, means they have the feature enabled in their current driver.

    They already have the Vega driver up and running (17.30-170711).

    [​IMG]
    This is completely different, the set of games tested have changed between launch of 480 and 580, some new games favored the RX480 more, other favored NV more.
    They also didn't claim any significant performance increases after enabling the feature, they also released final performance targets for their hardware which were not that different from Vega FE. We can't draw sweeping conclusions if the vendor isn't willing to draw any.
    It's plausible. Just not plausible now at launch when AMD themselves are implying otherwise.
     
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  16. 3dilettante

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    It's certainly true that the complexity of these systems is massive, but the difference between "could" and "should" is increasing in the current competitive climate.

    One could judge a vendor by how often and how badly they do this, as a measure of how likely they are to re-offend, or how much they are willing to accept as payment for an incomplete product.


    I think it's plausible that Nvidia and Intel's engineers considered an opportunistic hybrid tiling solution with hidden surface removal around the same time or earlier than AMD.
    They may have also had a good idea of the complexities or shortcomings that would be encountered.

    Nvidia, at least, went with a specific form of tiling, but not with the complexity adder of full HSR. That might point to one call being the better one.
    I've been mulling over whether the date of AMD's patents on the concept may have meant it missed the level of adoption of more deferred engines or things like the visibility-buffer based engine concepts.
     
  17. leoneazzurro

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    AFAIK I've read somewhere this is emulated in software and not being a (complete) HW based solution. But I'm afraid I cannot find again where I read that.
     
  18. CarstenS

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    Is this like the „Fermi is doing tessellation in software“-software discussion? Or is it coming from the discussion whether or not the roughly corresponding Open CL limit is a hard limit or software enforced?
     
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  19. leoneazzurro

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    As I told you, i only read this somewhere. Anyway, if true, it is probably the second option.
     
  20. ToTTenTranz

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