AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion
Maxwell TBR has been enabled for a long time before the tool David used existed, debugging or not.
Just few quotes from Raja AMA to remind you about few things:
Make of that what you will
RX will be fully optimized gaming drivers, as well as a few other goodies that I can't tell you about just yet....But you will like FE too, if you can't wait
Many argue that vega is just a refined polaris gpu, how would you respond to this ?
My software team wishes this was true
Vega is both a new GPU architecture and also completely new SOC architecture. It's our first InfinityFabric GPU as well
Make of that what you will
It was advertised as a feature of Vega architecture, but it's quite common, that not all features are enabled on all products. E.g. GCN / Pascal supports half-speed FP64, but many products have this feature disabled (by hardware or software). AMD didn't release any technical presentation of Vega FE. In fact they avoided to state, that FE supports TBR.
Although I doubt there will be major changes in a product launched a mere month from now, there is precedence for AMD products shipping with hardware features disabled.
Recall Bonaire. XDMA Crossfire, TrueAudio & non-DisplayPort triple-monitor were all features of the silicon but weren't enabled until the 260X launched 6 months after the 7790. However, those were niche features.
Recall Bonaire. XDMA Crossfire, TrueAudio & non-DisplayPort triple-monitor were all features of the silicon but weren't enabled until the 260X launched 6 months after the 7790. However, those were niche features.
Her is the Radeon Vega Frontier Edtion
http://pro.radeon.com/en-us/product/radeon-vega-frontier-edition/
http://pro.radeon.com/en-us/product/radeon-vega-frontier-edition/
Cache hitrate is a valid point, yes. But on a single-colored full screen quad as many fillrate tests use (or 2x2 textures and the like), that would not be an issue at all contrary to more real-world applications.
Exactly. Vega - as per the techreport quote earlier - seems to be able to switch back and forth between both rasterizers, thus showing no trace of binning if the traditional option is used (or - at your discretion - the DSBR is not enabled in the driver). If you don't want to implement both options in hardware though, you could have a kind of passthrough mode through your TBR, basically a compatibiility mode (for whatever reasons) where you do not bin and do not tile.
For completeness sake, I never said you said.I never said it is proof. I always wrote about what appears to be the case. And I explicitly hedged my bet and offered two possibilities:
They say nowhere that the GPU has a TBR. They just say an improved Rastering Technology. Whatever that means.
Nice find. Anyway, they just said it was "updated", but there is not a single mention of Draw Stream Binning Rasteriser or tile-based rasterisation.
It was definitely something touted back in January
http://techreport.com/review/31224/the-curtain-comes-up-on-amd-vega-architecture/3
http://techreport.com/review/31224/the-curtain-comes-up-on-amd-vega-architecture/3
Because you can have game compatibility issues, I'd imagine. I suspect this will be enabled on a per-game basis for quite some time before it becomes the primary method and the legacy method is used as a fallback for games which are known to have troubles.
LOL. It is based on Vega, but not on Vegas feature set. That would be a new dimension. Thinking GF4MX.
Are you saying Frontier Edition's chip is completely different than RX Vega?
DavidGraham
Veteran
All they did say that FreeSync was off. Besides, turning on V.Sync to hide comparative performance between you and your competitor is a new low.
Rather the opposite, Vega FE must have TBR, because they are the same silicon.
Albeit it has to be said the "shade once" part (i.e., HSR) cannot work with the UAV counter used in this code (as that's certainly a side effect which would change the rendered result). But that should work independently from the actual binning part I'd hope...
(Maybe pipeline statistics queries would allow HSR, though I'm not even sure of that.)
One possibility why binning may not be enabled could be that the driver disables it due to the UAV, even if it should not be necessary. Or maybe it's really just completely disabled for now.
(Maybe pipeline statistics queries would allow HSR, though I'm not even sure of that.)
One possibility why binning may not be enabled could be that the driver disables it due to the UAV, even if it should not be necessary. Or maybe it's really just completely disabled for now.
No, of course not, just wondering aloud what that argument in the posts leading up could mean in the end. To be clear: I cannot imagine that this would be the case.
ok good
Considering the intended target audience for the Frontier Edition (game developers), you would think that promoting a new binning rasterizer would be there. Likely just an unintended omission, or tin-foil hat drama it's not working properly and has been turned off. We'll find out with RX Vega I guess.Did any pro site receive a sample from AMD? ;-)
Remember this slide:
http://www.thinkcomputers.org/all-n...ia-geforce-gtx-1080-pascal-crafted-for-speed/
I've done my share of pushing an small part of an existing chip to higher clocks by painstakingly working my way from the top to the bottom of the timing violation report file. The vast majority of changes are through RTL modifications, but replacing or moving individual standard cells in the layout can give significant improvements as well, on the same process.
(It sounds really boring work, but there's a large amount of satisfaction to be had knowing that you defeated a tool. Like writing x86 assembler and coming out ahead against a C compiler.
)For Vega, AMD may have done both: a new architecture *and* this kind of detailed optimizations.