AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

Discussion in 'Architecture and Products' started by ToTTenTranz, Sep 20, 2016.

  1. Digidi

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    What i mean if you see the Advantage nvidia did from Kepler to Maxwell. (From Intermediate to tiled based rastizer) you will get my Point. Saves a lot of energy and dosen't argue the shader with workloads which are not needed.
     
  2. Samwell

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    Maxwell was a redesign of the shader core. It's impossible to say how much of the gains were from tiling and how much from the new shader core. Vegas NCUs at the moment just look like the old CUs with 2xFP16 added.
     
  3. Digidi

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    Vegas NCUs must be different. How will you reach 1.6 Ghz whiout Major changes inside the CUs?
     
  4. CarstenS

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    What would be the benefits of a TBDR in a scene/engine, which does it's own HSR with a z-prepass for example.
    Or in a synthetic test, that just renders a plane of two large quads to measure pixel fillrate, for that matter. I cannot think of any, and the binning stage would be unnecessary at best and a bottleneck at worst (depending on it's actually modus operandi). So, if you have the chance to turn your DSBR on and off based on a reasonably working detection scheme, I'd call that an advantage.
     
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  5. Digidi

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    But the most games are now optimized for Nvidia. That means the most games prefere a Tiled Base Rasterizer. Why not follow this way?
     
  6. Gipsel

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    Digidi likes this.
  7. Clukos

    Clukos Bloodborne 2 when?
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    How did you end up to that conclusion? Most games are just ports from the console version, all of which (Ps4/X1/Ps4Pro/X1X) are using GCN GPUs.
     
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  8. CarstenS

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    I fail to see the connection between a synthetic tool which might be detected (whether or not correctly remains to be seen) by the driver as not profiting from DSBR and games that allegedly "prefer TBR because they are optimized for Nvidia" (UE and Cryengine for example would like to differ).
     
  9. CarstenS

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    The fallback can be implemented differently, I guess. Two rasterizer methods or one, which has a "do not sort" option, but traverses the binning buffer nevertheless. And of course we could be looking at a simply misdetected application behaviour.

    In short: I am not yet convinced that the DSBR is completely inoperable with current drivers. That would be a major eff-up for AMD, since performance results WERE bound to be published regardless of the state the card and it's drivers are in right now.
     
  10. TurpoUrpo

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    You would not want "PRO" card to have any instability would you? If there is some issues, they would be wise to restrict that issue from happening. It's not so important on game cards is it? So basically "betatest" with RX Vegas.

    I meant to quote this:
    Cant find edit..
     
    #2490 TurpoUrpo, Jun 30, 2017
    Last edited by a moderator: Jun 30, 2017
  11. CarstenS

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    Not sure if i would agree. I don't want stability issues on my PC in general. Just think of competitive e-sports, where real money might be at stake. And "Pro" is, as has been discussed at length earlier, not the same as "WX".
     
  12. Malo

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    Process shrink? 14nm vs 28nm on the Fury X. Performance metrics so far basically make it a 14nm Fury X with seemingly no other optimizations or differences.
     
  13. pharma

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    Believe Ryan mentioned running professional tests overnight (takes 12 hours) and should have the results when the live stream continues sometime this morning.
     
  14. kalelovil

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    Polaris is already on 14nm and can barely reach 1.5Ghz on liquid cooling.

    Vega's die size is considerably larger than a Fiji shrink should be.
     
  15. Gipsel

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    The z prepass could be a bit faster. And that prepass basically populates the z buffer (and the early-z metadata connected to it) so the early-z rejection can operate near peak efficiency in the following pass. But a TBDR should be even more efficient than that. And also the limited binning of Maxwell/Pascal or supposedly Vega can bring additional benefits (you can reject stuff even earlier than with an early z test).
    Even for a simple fillrate test (which often draws full screen quads back to front [or with switched off z test] to reduce the overhead for a new frame) a tile based binning offers the benefit of increased cache hitrate and (depending on the circumstances but potentially vastly) reduced bandwidth requirements (for all cases which aren't ROP bound but bandwidth bound, i.e. blending or fp16 framebuffers [transparent stuff]).
    If it would bin (even without any sorting/hidden surface removal stuff Vega is supposedly capable of), the chip would work on all buffered geometry in a bin (or two or four, depending how many fit the caches simultaneously) before starting the next tile. That is definitely not visible with Vega in this triangle bin test. The geometry appears not to be binned at all, it is processed serially and not binned in tiles.
    I never said it is proof. I always wrote about what appears to be the case. And I explicitly hedged my bet and offered two possibilities:
    ;)
     
    #2495 Gipsel, Jun 30, 2017
    Last edited: Jun 30, 2017
  16. TurpoUrpo

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    Well, i meant that the level of acceptable instability is different. Naturally it should still be rare to be acceptable for gaming cards and not anything that results in crash of the card, but maybe some picture quality related stuff.
     
  17. Malo

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    And Vega has been "optimized" for higher clocks, which is one new feature I guess, but still on normal operation (FE) operates around 1.4Ghz without additional cooling being applied for sustained higher clocks. My point is that so far it's operating like a Fury X at much higher clocks.

    And has several new features as well. HBCC hasn't been tested since reviewers weren't sent any cards so we don't know how well that operates in memory management, we'll see more focus on that when RX Vega is released. Otherwise, for such a large chip, it doesn't seem to be performing as such.

    Drivers? Some features not working right yet? Who knows. We'll know more at SIGGRAPH.
     
  18. Ryan Smith

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    Indeed, and controlling/triggering that is the big breakthrough that David Kanter made in order to prove there's TBR. When you're using standard debug tools, TBR isn't (or at least at the time, wasn't) turning on, possibly because NV wanted to hide it, but more likely because they didn't want TBR getting in the way of debugging. TBR is meant to be transparent to the developer.
     
  19. Leier

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    Okay, so AMD had the card at their developers for over half a year. They even showed prototypes in january. So it is not like they did not have cards at all or too few. So i don't see why TBR shouldn't work at all after over half a year of development and should be working in 6 or 8 weeks when the consumer cards show up.

    What if, just as a scenario, the TBR is broken on the hardware? Some bug which causes it to not work. And maybe AMD is still working on a bug fix or even maybe does not find one.

    Do we have a stepping from the currently sold FE cards?
     
  20. Digidi

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    @Leier

    I don't think so. If there is a big bug inside rasterizer they will not Launch the product. Its one of the main Features of the product and its advertisted allready. If its not working on Hardware they will not sell it.
     
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