AMD Vega 10, Vega 11, Vega 12 and Vega 20 Rumors and Discussion

I agree. But then I don't understand why there is no support in the current driver. If it is such an important feature, this part of the driver should be working properly for at least 2-3 months.
 
Indeed, and controlling/triggering that is the big breakthrough that David Kanter made in order to prove there's TBR. When you're using standard debug tools, TBR isn't (or at least at the time, wasn't) turning on, possibly because NV wanted to hide it, but more likely because they didn't want TBR getting in the way of debugging. TBR is meant to be transparent to the developer.
Maxwell TBR has been enabled for a long time before the tool David used existed, debugging or not.
 
Just few quotes from Raja AMA to remind you about few things:

Developing drivers for new architecture is one of the most complex and difficult engineering tasks for a GPU company...In fact this is one of the reasons why there are only so few GPU companies.

Consumer RX will be much better optimized for all the top gaming titles and flavors of RX Vega will actually be faster than Frontier version!

RX will be fully optimized gaming drivers, as well as a few other goodies that I can't tell you about just yet....But you will like FE too, if you can't wait:)

The Frontier Edition was designed for a variety of use-cases like Machine Learning, real-time visualization, and game design. Can you play games on Frontier Edition? Yes, absolutely. It supports the RX driver and will deliver smooth 4K gaming. But because it is optimized for professional use cases (and priced accordingly), if gaming is your primary reason for buying a GPU, I’d suggest waiting just a little while longer for the lower-priced, gaming-optimized Radeon RX Vega graphics card

Many argue that vega is just a refined polaris gpu, how would you respond to this ?

My software team wishes this was true:)
Vega is both a new GPU architecture and also completely new SOC architecture. It's our first InfinityFabric GPU as well

Make of that what you will :)
 
@Leier

I don't think so. If there is a big bug inside rasterizer they will not Launch the product. Its one of the main Features of the product and its advertisted allready. If its not working on Hardware they will not sell it.
It was advertised as a feature of Vega architecture, but it's quite common, that not all features are enabled on all products. E.g. GCN / Pascal supports half-speed FP64, but many products have this feature disabled (by hardware or software). AMD didn't release any technical presentation of Vega FE. In fact they avoided to state, that FE supports TBR.
 
Although I doubt there will be major changes in a product launched a mere month from now, there is precedence for AMD products shipping with hardware features disabled.

Recall Bonaire. XDMA Crossfire, TrueAudio & non-DisplayPort triple-monitor were all features of the silicon but weren't enabled until the 260X launched 6 months after the 7790. However, those were niche features.
 
The z prepass could be a bit faster. And that prepass basically populates the z buffer (and the early-z metadata connected to it) so the early-z rejection can operate near peak efficiency in the following pass. But a TBDR should be even more efficient than that. And also the limited binning of Maxwell/Pascal or supposedly Vega can bring additional benefits (you can reject stuff even earlier than with an early z test).


Even for a simple fillrate test (which often draws full screen quads back to front [or with switched off z test] to reduce the overhead for a new frame) a tile based binning offers the benefit of increased cache hitrate and (depending on the circumstances but potentially vastly) reduced bandwidth requirements (for all cases which aren't ROP bound but bandwidth bound, i.e. blending or fp16 framebuffers [transparent stuff]).
Cache hitrate is a valid point, yes. But on a single-colored full screen quad as many fillrate tests use (or 2x2 textures and the like), that would not be an issue at all contrary to more real-world applications.

If it would bin (even without any sorting/hidden surface removal stuff Vega is supposedly capable of), the chip would work on all buffered geometry in a bin (or two or four, depending how many fit the caches simultaneously) before starting the next tile. That is definitely not visible with Vega in this triangle bin test. The geometry appears not to be binned at all, it is processed serially and not binned in tiles.
Exactly. Vega - as per the techreport quote earlier - seems to be able to switch back and forth between both rasterizers, thus showing no trace of binning if the traditional option is used (or - at your discretion - the DSBR is not enabled in the driver). If you don't want to implement both options in hardware though, you could have a kind of passthrough mode through your TBR, basically a compatibiility mode (for whatever reasons) where you do not bin and do not tile.

I never said it is proof. I always wrote about what appears to be the case. And I explicitly hedged my bet and offered two possibilities:
;)
For completeness sake, I never said you said. ;)
 
It was definitely something touted back in January

http://techreport.com/review/31224/the-curtain-comes-up-on-amd-vega-architecture/3

dsbr.png
 
But this make no sens. The draw-stream binning rasterizer have always an Advantage above a common rasteriezer. Why avoid them?

Because you can have game compatibility issues, I'd imagine. I suspect this will be enabled on a per-game basis for quite some time before it becomes the primary method and the legacy method is used as a fallback for games which are known to have troubles.
 
Is it? Did PC World state whether or not VSync was off? I mean, I couldn't tell 60 fps from 60fps in a single-GPU setup most of the time.
All they did say that FreeSync was off. Besides, turning on V.Sync to hide comparative performance between you and your competitor is a new low.
Are you saying Frontier Edition's chip is completely different than RX Vega?
Rather the opposite, Vega FE must have TBR, because they are the same silicon.
 
Albeit it has to be said the "shade once" part (i.e., HSR) cannot work with the UAV counter used in this code (as that's certainly a side effect which would change the rendered result). But that should work independently from the actual binning part I'd hope...
(Maybe pipeline statistics queries would allow HSR, though I'm not even sure of that.)
One possibility why binning may not be enabled could be that the driver disables it due to the UAV, even if it should not be necessary. Or maybe it's really just completely disabled for now.
 
Are you saying Frontier Edition's chip is completely different than RX Vega?
No, of course not, just wondering aloud what that argument in the posts leading up could mean in the end. To be clear: I cannot imagine that this would be the case.
 
No, of course not, just wondering aloud what that argument in the posts leading up could mean in the end. To be clear: I cannot imagine that this would be the case.
ok good :) Considering the intended target audience for the Frontier Edition (game developers), you would think that promoting a new binning rasterizer would be there. Likely just an unintended omission, or tin-foil hat drama it's not working properly and has been turned off. We'll find out with RX Vega I guess.
 
Polaris is already on 14nm and can barely reach 1.5Ghz on liquid cooling.
Remember this slide:
http://www.thinkcomputers.org/all-n...ia-geforce-gtx-1080-pascal-crafted-for-speed/

I've done my share of pushing an small part of an existing chip to higher clocks by painstakingly working my way from the top to the bottom of the timing violation report file. The vast majority of changes are through RTL modifications, but replacing or moving individual standard cells in the layout can give significant improvements as well, on the same process.

(It sounds really boring work, but there's a large amount of satisfaction to be had knowing that you defeated a tool. Like writing x86 assembler and coming out ahead against a C compiler. :) )

For Vega, AMD may have done both: a new architecture *and* this kind of detailed optimizations.
 
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