You guys need to take a chill pill. Put your blinders on and ignore what AMD does with their partners, especially as it was rather obvious to begin with that no partner session would include unreleased details. (AMD is very fond of not getting sued by their investors)
Why would AMD communicate with their partners through their main twitter account? It makes no sense.You guys need to take a chill pill. Put your blinders on and ignore what AMD does with their partners, especially as it was rather obvious to begin with that no partner session would include unreleased details. (AMD is very fond of not getting sued by their investors)
When they're ready to let us know what's going on, they'll tell us directly.
Because they're trying to hype up their partners. Partners can be very encompassing, everything from a few high-level board engineers at Sapphire and the like, right out to retail salespeople.
Oh yeah? What's your idea of getting a grip then? Agree with AMD's apparent tactics of letting NV get all the hype and good press for the foreseeable future? Sounds like a winning strat for a player who is already on the ropes!
While I have no doubt believing AMD partners are just human beings and behave as such (understatement of the century
) let me highlight the absurdity of hyping up hundreds of people by sending the wrong message to a few hundred thousands more.Were there similar register pressure issues pre-Pascal? I know register pressure is always something you like to avoid for CUDA, but I don't know what extent game developers struggle with it.
My understanding is that it executes a wave of 64 as 4 cycles on a 16 wide SIMD. I understand how the wave of 64 can give utilization issues when there's thread divergence, but once you accept that, does it matter whether or not that 64 wide wave gets executed in 1, 2 or 4 cycles? That's just an implementation issue, isn't it?
Hype will not deliver sales, The fact Polaris and GP104 seem to occupy completely difference market segments with maybe the top of polaris overlapping with the bottom of GP104 makes your kind of position even more bizarre. So what exactly should one be doing, lets not forget you cant even buy a GP104 yet, the 1070 which is the only Part of GP104 that polaris might compete with launches even latter then the 1080 and well after computex.Oh yeah? What's your idea of getting a grip then? Agree with AMD's apparent tactics of letting NV get all the hype and good press for the foreseeable future? Sounds like a winning strat for a player who is already on the ropes!
I guess it's just surprising how big a difference there is between the tight communication ship that is Nvidia and left-hand-doesn't-know-what-right-hand-is-doing at AMD.
That's correct. Also by switching to 32 wide wavefronts while keeping the same register file size per wavefront would effectively double the per thread register file but it would cut the total number of threads in half.
Well, assuming you're correct, the lack of it sure as fuck won't either, I think you can agree, yes?
Oh yeah? Lemme tell you what's bizarre; that people wouldn't get influenced by NV's awesome paper-launched hardware, and instead patiently and dutifully wait for whatever tiny morsels of information AMD deems fit to dole out at their leisure - weeks later! Add to the broth; mixed messages, and multiple conferences - the first of which apparantly for no genuinely good reason at all, AMD readily admits. So how's that for bizarre for you?
Doesn't matter, because A: GP104 cards will be for sale before AMD has even presented their counter-offer, and B: chances are pretty good that 1070 cards will be for sale no later than polaris 10 cards, AND beat the snot out of them as well - especially where driver quality is concerned.
Too bad we have to rely on rumors for AMD information, while NV has already shown their wares in public. AMD, who bragged last year they were ahead, and had an aggressive schedule and whatnot. They teased these cards back in friggin december, and since then - nothing. Even after NV's nuclear bomb of a presentation.
Why don't you tell me, instead of asking rethorical questions?
(That and NV hardware often being just plain faster - with a few notable exceptions.)That's not correct. First of all NVIDIA and AMD physical SIMD width is the same (i.e. 16 lanes) and have the same likelihood of hitting or missing data caches (if they used the same cache design, that is
) per clock. Of course the total number of CUs or SMs determine how many outstanding memory accesses you can have. The same trick works if you have the register file banks serve a subset of all registers for the whole logical SIMD width. You can get collisions and stalls from time to time but I suspect they can be greatly minimized if the compiler knows about the register banks. Moreover everything your logical SIMD is wider than your physical SIMD and you need more than one clock to operate on the whole vector than the probability of collisions becomes truly negligible. I suspect both INTEL and NVIDIA use similar techniques instead of using multi-ported register files.
NVIDIA physical SIMD width has been 32 since Kepler.
I don't think the tweet is meant to be hyping. Rather it's meant to get them to come to the training session where said hype will be dispensed.If AMD thinks their partners can be hyped with a tweet, they must not think very highly of their own partners...
(They also apparently believe people susceptible to twitter hype don't read Reddit...
That card is going to keep the "mythical new king status" regardless, because reportedly AMD won't have anything to counter it until somewhere in 2017 (or at best, if the latest rumors turn out correct, for another 5 months).
