That's not really necessary: the core transaction scheduling is the almost the same for all anyway. The only difference is the PHY side. Almost all memories system implantations that I've seen in there last decade separate the scheduler from the PHY.I'd really have to look into the specs for the memory controllers more, but in theory it would be advantageous to develop a controller that could support them all.
From a scheduler point of view, a single HBM stack would look like bunch (8?) GDDR5 chips. Nothing else.
That would make very little sense.The base die for HBM could also integrate part of the controller or possibly a minimally active interposer.
The latency of all DRAM technologies of the same generation is essentially the same.Power/latency of the HBM should be far easier to drive than the GDDR5.