Actually, I just had again a look on those strings in the driver. And it looks like I misinterpreted that a bit last year. The wording changed and is quite unambiguous now ("HW doesn't support trans unit slot" instead of "An ALU instruction was issued to the scalar slot. This feature is scheduled for removal in Northern Islands!" in Cat 9.8).
Ooh, tasty.
At face value that seems to imply that the next chip is NI. Which would imply that SI was cancelled. But what if SI comes after NI or SI was a mirage or NI is in there as well as SI, but HD6xxx is SI. Oh and what happened to Hecatoncheires?
Some rumours suggest that NI followed SI quite closely, i.e. well within one year.
Also, if x86 APU is supposed to get an annual refresh to the GPU section, then what we could be seeing is first APU being Evergreen based then second version being NI-based, skipping SI. Lead time on APU (tape-out to retail) is ~twice GPU so it seems likely that some skipping would be required to deal with the 40nm fuckup and the cancellation of 32nm (for GPUs).
i.e. the GPU roadmap has been redrawn so much that the APU guys have picked on something not caught in the middle.
So it really looks like NI is a pure 4 slot design. But the 4 slots are not created equal, the w (merged with t?) unit can't process a few instruction. I don't know which ones are missing, but generally it looks almost like the t slot today.
In Evergreen there are slight differences between the XYZW lanes - this is because of pairings and other intricacies in some of the new instructions. So the difference you're seeing for W might be nothing more than that.
Also, if there really is no "transcendental" lane, then sub-functions of transcendental computation would be spread asymmetrically across the other lanes. And there's always the possibility that transcendentals are a macro (just like double-precision divide is a macro - or, indeed, like a 1-ULP SIN or COS is a macro).
By the way, what do you expect from things like "SET_PRIORITY__NI", "INTERRUPT_AND_SLEEP__NI" or "INTERRUPT__NI"? A step in the direction of better managed multitasking on a GPU?
Ooh, more tasty stuff. Allowing the driver/operating system to stop one kernel/application totally killing responsiveness.
And NI gets int24 multiplication in the ALUs, not only uint24 like Evergreen (which is still not usable from IL, isn't it?).
I've not seen uint24 so far.
Also, while I'm at it, it's been suggested that the SIMDs would be 24 wide instead of 16 wide, in order to keep a 20-SIMD design. 1024 work items is the upper limit on workgroup size - that and other common power-of-two workgroup sizes don't accord with multiples of 24.
If a shader engine remains at 10 SIMDs, with 16 ROPs, then 30 SIMDs (each of 64 ALU lanes) sort of matches up with having a 384-bit bus, i.e. 48 ROPs
Each shader engine presumably has quite a bit of "control" overhead. The way the die shot of RV770 shows things, it's extremely hard to see how much overhead there is. We can see the ALUs and TUs, but I can't work out how much of the "uncore" is the stuff that makes a shader engine work (the Sequencer). Obviously the more shader engines, the more of this overhead. And there's other overheads for integration of each SE into the entire GPU.
Anyway, generally speaking, increasing the count of SEs is going to lower the per-mm² ALU efficiency. So some of the gain in efficiency due to increased ALU utilisation with 4 lanes instead of 5 is going to be lost with both the increased count of SIMDs and the likely increased count of SEs. Though 2 SEs, each of 15 SIMDs, is theoretically an option.
