AMD: R9xx Speculation

Yes. The differences from a VLSI perspective between SOI and bulk are fairly minimal. The primary issues with SOI start to show up when dealing with highly dynamic and analog circuits.

 

Well, considering there are a lot of senior people on both sides who used to work at the same company (DEC/Digital Semi).

 

Cuba, Turks and Caicos, southern Bahamas, Caymans, and Hispaniola are all roughly at the same latitude.

Ibiza, Mallorca, Menorca, Sardinia, Sicily, and a couple in the Aegean Sea.

 

http://www.semiaccurate.com/forums/showpost.php?p=40266&postcount=99

 

With huge being reserved for anyhting Nvidia?

 

Anything smaller than Nvidia isn't huge by Nvidia standards.

 

Lixian said the first chip out will have area less than 400mm2. So huge prolly doesn't apply there.

However, if you have some insider info contradicting it you are most welcome to share it with us or PM it to me.

 

The only thing they need to fix is the tesselation in short term. They need to boost the performance litle over GTX480 and reach full triangle rate in any tesselation case. And that could be done with near cypress die size and architecture tweaks.
GF100 on 40nm is a dead fish. No x2 card, respin unlikely. They could make maybe a higher clocked 256SP part (with 64 TMUs) and make a X2 card from it.(and get a higher clocked 512sp card with 128 TMUs and maybe 2*256bit bandwith)

 

I'm not sure a Cypress refresh (Southern Islands?) needs to be faster than GTX 480 in tesselation, just as long as it is faster than it is currently, IE - at least able to reach theoretical speeds in benches where it seems to be limited by something for some reason. If it's currently limited to 1/3 to 1/6th speed in certain situations getting it to run at full speed will already be quite a boost for a refresh part.

Although I'm sure Mintmaster would love to see it go to at least 2 triangles/clock setup.

Regards,
SB

 

It's because the properly ludicrous, entirely codename based, speculation, coming to a 'news' site near your as fact real soon now, surely surely has to be:

Southern Islands: R9xx on GloFo 32nm SOI process
Northern Islands: (aka Not Southern Islands) R9xx on TSMC [strike]32nm[/strike] (Oops!) Bulk process

 

Caveman Jim might hit close with his speculation on SI and NI being (almost) the same thing.

 

maybe SI is NI@40nm and the "true" NI is 28nm? .... and there is no "hybrid" of NI and cypress called "SI"? mayby SI is just a big "real" NI?

 

That could very well be the case.

From the bits of info and rumors that float around, I believe the situation is something like this:
TSMCs "40nm" process is essentially their full-node, basically their 45nm process with a few tweaks and renamed for bragging/marketing reasons.
TSMCs "32nm" process, despite carrying a number that other foundries use for their next-gen full-nodes, was actually just a half-node, an optical shrink of the "40"nm process.
NI was supposed to be the new architecture made on the "32"nm half-node process (similar to R580 90nm -> R600 80nm).
When TSMC decided to cancel their 32nm half-node, AMD had to port back their NI designs to the 40nm parent process, since scrapping the 40/32nm version of the Islands generation completely and concentrating on 28nm would have been too risky. Since this might have forced them to make a few changes, they (re-)named the chip series Southern Islands instead.

This would mean NI in its originally intended form won't happen, and that the N. Islands naming scheme will either be (re-)used for the 28nm full-node shrink of SI instead or maybe even not used at all (Hecato...something may actually be the name of the 28nm generation then, shrinked SI with minor tweaks and significantly more SIMDs perhaps?).

 

TSMC's 40nm is the half node optical shrink as is 28 nm. They're taking the same approach for the next node and skipping straight to 20nm.
http://eetimes.com/news/latest/showArticle.jhtml?articleID=224400067

 

Talk is cheap ... frankly I only trust Intel to get to 22 nm on time (pixel based PSM looks like a big leap forward, and they are the only ones making it).

 

Bears the question why Intel itself then planned LRB Prime on 45 and not 32nm. Except of course if this thread is mostly about SoCs and not standalone GPUs.

 

Considering the problem with 40nm TSMC seem to find it easier to jump nodes rather than do them. Maybe that's the reason then, you can't have any problems with a process size if you don't do it

 

You guys remember TSMCs 130nm process? It also did not start too well, but turned out pretty well, when the process matured. Maybe we should wait for FAB14 beofre making a final judgement.

 

Mass-producing such a large chip on a completely new process would be very risky, even for Intel. Besides, I think that according to Larrabee's original schedule, it was supposed to be released before the 32nm process would be ready.