AMD: R9xx Speculation

[Mindfury]

I just want to say that u could see much more difference with the 384bit when the whole gpu would be designed round it.

If ATI decide to increase ALUs amount significantly,then wider bus is necessary.Otherwise 256bit bus is enough.

 

[Jawed]

Remember that the memory system has its own clock domain.

Jawed

 

[Jawed]

Wafer Supply Agreement

http://www.xtremesystems.org/forums/showpost.php?p=4261808&postcount=25

So when that was written there was a clear intention to ramp up GPUs at GF. Since I'm getting bored by roadmap shuffles at both TSMC and GF, I'll let others argue over what the Wafer Supply Agreement says/means now.

Jawed

 

[GZ007]

If ATI decide to increase ALUs amount significantly,then wider bus is necessary.Otherwise 256bit bus is enough.

ALU-s would be crawling if they would need to depend on the 256bit gddr5 rather than the caches.
GF100 has 33.6 GPixel/s fillrate for the 384bit bus. That would be 240 GB/s bandwith if the memory controller would work as they planed. (GF100 seems to be limited with the cripled bandwith as some SLI results show over 100% scaling)
I could imagine a 36 ROP(850 MHz) 384 bit bus on gpu with cypress die size.

 

[liolio]

I hope that ATI will hold true to their "sweet spot strategy" and build more of a juniper++ than a cypress++. It would not be wize to take too much risks now especially as crossfire/X2 perfs scaling get better and better.

 

[CarstenS]

I could imagine a 36 ROP(850 MHz) 384 bit bus on gpu with cypress die size.

That's not a nice number. And every necessary crossbar really costs you more die space.

 

[3dilettante]

They could also change the ALU clocks like nvidia did long ago. ROP-s and TMU-s are likely bandwith bound but ALU-s usualy not.

The TMU and ALU sections are very tightly linked. Their inputs into the register file fit into how the SIMD's pipeline works, with 1 TMU input cycle per 3 ALU cycles.
The ALU clocks are not free to speed ahead without changing the pipeline.

 

[ferro]

I could imagine a 36 ROP(850 MHz) 384 bit bus on gpu with cypress die size.

Would 334 mm2 (or thereabout) allow for a 384 bit crossbar bus? It seems that the 50% additional bandwidth would be more than welcome at this point and in the near future.

 

[GZ007]

That's not a nice number. And every necessary crossbar really costs you more die space.

Yes but its still cheaper than 384bit with 48 ROP-s or 512bit with 64 ROP-s. They will need to sacrifice something or just go again with 256bit.
I think that for Eyefinity or for high resolution AA+adaptive AA the +50% bandwith could just help.

 

[TKK]

According to B3D benchmark,5870 is not bandwidth limited.

I'm pretty sure ATI won't use weird bus like 384bit.512bit bus will cost too much die space.I think they will stay with 256bit bus this year.

tbh, personally I think the B3D benchmark actually proves that the 5870 is somewhat bandwidth-limited. Sure, performance doesn't scale linearly with increased memory clock, but it does increase, and not just by 1% per 10% higher memory clock. The 5xxx cards may not be as bandwidth-limited as it was originally thought, but they're definitely more bandwidth-limited than for example the 4870/4890 and GTX 200 cards. I'm quite sure that if you took the 5870 and somehow managed to increase bandwidth to twice the 4890s bandwidth (matching the SP/TMU/ROP increase), you would see far better scaling than just 40-50% in most benchmarks. More like 60-70%, I would guess (in benchmarks that aren't CPU limited at that point, of course).

But I agree, I also doubt we'll see more than a 256-bit memory interface from AMD in the near future. With 7Gbps GDDR5 going into mass-production this year, 256 bit should be sufficient for a while.

@GZ2007:
neither AMD nor Nvidia have ever used a number of ROPs that isn't 1/8, 1/16, 1/32 or 1/64 of the interface width. For a 384-bit interface, they would go with either 24 or 48 ROPs. Besides, as far as I know, in today's GPUs the ROPs only account for a relatively small area of the die, so removing 12 ROPs wouldn't help much.

 

[Squilliam]

So what are the chances that this uncore rejig which Charlie aludes to if true means that they are going to eliminate the ROP units? Its the ultimate flexibility and its one of the first steps away from a pure raster card to a hybrid.

 

[GZ007]

But I agree, I also doubt we'll see more than a 256-bit memory interface from AMD in the near future. With 7Gbps GDDR5 going into mass-production this year, 256 bit should be sufficient for a while.

Yes its much more likely that AMD goes with 256bit.
Also with 256bit they will be stuck with 1024 MB or 2048 MB video ram. Anandtech Eyefinity 6 http://www.anandtech.com/show/3621/amds-radeon-hd-5870-eyefinity-6-edition-reviewed/6 shows that it helps only with min framerates in crysis warhead (altough they could try out more demanding games like metro 2033). But future games pushing texture,shadow resolutions to limits running in deferred rendering mode could make 1024MB not enough in high resolutions. (metro 2033 destroys the radeons after 1920*1200 with AA/AF http://www.pcgameshardware.com/aid,...Fermi-performance-benchmarks/Reviews/?page=13)

 

[rpg.314]

So what are the chances that this uncore rejig which Charlie aludes to if true means that they are going to eliminate the ROP units? Its the ultimate flexibility and its one of the first steps away from a pure raster card to a hybrid.

ROPs aren't going anywhere in SI.

 

[rpg.314]

What is so weird about a 384 bit bus?

 

[CarstenS]

Yes but its still cheaper than 384bit with 48 ROP-s or 512bit with 64 ROP-s. They will need to sacrifice something or just go again with 256bit.

I'm no chip design expert (heck, I'm no expert at all) but I`m not sure about 256b/48 ROPs with a newly designed caching system plus a full 12x12 crossbar would really be that much cheaper. But we'll see.

 

[Squilliam]

Yes its much more likely that AMD goes with 256bit.
Also with 256bit they will be stuck with 1024 MB or 2048 MB video ram. Anandtech Eyefinity

Hynix Semiconductor has announced the industry’s first 2Gb GDDR5 chip that can operate at unprecedented 7GHz effective clock-speed. The memory maker claims that the new chip with never-before-seen performance will be in demand already in the second half of 2010.

The newly developed GDDR5 is the fastest and highest density graphics memory available in the market. It operates at 7GHz effective clock-speed and processes up to 28GB/s with a 32-bit I/O. In addition to its fastest speed and highest density, it is also designed to minimize power consumption with 1.35V operation voltage. Thanks to 40nm process technology, the device reduces energy consumption by 20% over the preceding memory solutions using 50nm class technology.

2Gb GDDR5 memory chips will enable graphics cards with 2GB or more of onboard memory with 224GB/s or higher peak bandwidth. It can be assumed that Hynix’s new memory chips will be used on the next-generation graphics cards from ATI, graphics business unit of Advanced Micro Devices, and Nvidia Corp., which are also due in the second half of next year.

Hynix plans to start mass production of 2Gb GDDR5 in the second half of next year to meet the increasing demand for high performance graphics DRAM.

I think they have it covered...

 

[Jawed]

@GZ2007:
neither AMD nor Nvidia have ever used a number of ROPs that isn't 1/8, 1/16, 1/32 or 1/64 of the interface width.

http://www.beyond3d.com/resources/chip/119



I'm posting this courtesy of such a quasimodo.

Jawed

 

[GZ007]

I'm no chip design expert (heck, I'm no expert at all) but I`m not sure about 256b/48 ROPs with a newly designed caching system plus a full 12x12 crossbar would really be that much cheaper. But we'll see.

I was posting about the posibility that they will wait with 384bit for 48 ROP card and 512bit for a 64 ROP single card which would cost more than just increase the bus width with same ROPs (at least the x2 cards have 2*256bit with 2*32 ROPs).
Not that they will have 256b/48 ROP card .

 

[GZ007]

Hynix Semiconductor has announced the industry’s first 2Gb GDDR5 chip that can operate at unprecedented 7GHz effective clock-speed. The memory maker claims that the new chip with never-before-seen performance will be in demand already in the second half of 2010.

The newly developed GDDR5 is the fastest and highest density graphics memory available in the market. It operates at 7GHz effective clock-speed and processes up to 28GB/s with a 32-bit I/O. In addition to its fastest speed and highest density, it is also designed to minimize power consumption with 1.35V operation voltage. Thanks to 40nm process technology, the device reduces energy consumption by 20% over the preceding memory solutions using 50nm class technology.

2Gb GDDR5 memory chips will enable graphics cards with 2GB or more of onboard memory with 224GB/s or higher peak bandwidth. It can be assumed that Hynix’s new memory chips will be used on the next-generation graphics cards from ATI, graphics business unit of Advanced Micro Devices, and Nvidia Corp., which are also due in the second half of next year.

Hynix plans to start mass production of 2Gb GDDR5 in the second half of next year to meet the increasing demand for high performance graphics DRAM.

They also forget to tell that someone needs to make a memory controller that works at those speeds fine (which could add to costs). Nvidia had problems to reach 4GHz on the first try

 

[neliz]

They also forget to tell that someone needs to make a memory controller that works at those speeds fine (which could add to costs). Nvidia had problems to reach 4GHz on the first try

Well, you could always make your controller ECC capable to offset all the erroneous bits in your high speed data transfers!

Oh, and NV had problems reaching 4Ghz on more than one try, don't worry! They're beavering away eagerly.