AMD: R9xx Speculation

[no-X]

Twice as long SIMDs? I think slightly higher ALU:TEX would be good, but 8:1 seems to be too much...

Anyway, R600, R7xx and R8xx are 4:1, but in fact R7xx lowered the ratio for some situations (less capable TMUs, half FP16 rate), R8xx lowered it again (by moving interpolation to SPs)... Wouldn't be 6:1 better? E.g. 80 TMUs + 2400 SPs?

 

[fellix]

With the current concept architecture, I don't see the benefit of widening the ALU:TEX ratio, and booming the batch size at the same time. It seems ATi is able to do very good job at shrinking the SIMD multiprocessors with each process manufacturing node, by eliminating redundant logic -- the beauty side of dense packed VLIW ALU lanes.

 

[Silent_Buddha]

Nah.., I am just wondering if the said factors will conspire to create a Fermi like situation.

Regarding Fermi's tessellation, it does seem over-provisioned, especially for something that is going to see only baby-usage for the most of it's life.

Well to be fair, theoretically a game could offer the user the ability to adjust the tesselation factor of objects/terrain perhaps? If that's true then it might still be possible to leverage the massive tesselation sooner rather than later.

However, if it came at the cost of sacrifices in other area's of the chip that might have been better for current workloads, we may have something similar to X1900 where the shader ratio is looking like it was great for future games. But unfortunately most of those future games came significantly later than the card's average time of ownership.

Either way, I like that it has massive tesselation power. But then again again, Tesselation is one of the biggest things I'm looking forward to. And if it's used as well as I hope it can be, I think Tesselation will be the biggest thing to hit 3D accerelerated rendering since the advent of programmable shaders in Dx9.0.

Of course, speaking to the chip itself, if can only be a slightly faster than Cypress coming 6 months later in limited quantities, well, how should I say this... I see a very short lived chip. Something similar to how quickly R600 was replaced and swepted under the carpet.

But I still love the tesselation power. And hope ATI's next product also has massive tesselation power.

Regards,
SB

 

[mczak]

Twice as long SIMDs? I think slightly higher ALU:TEX would be good, but 8:1 seems to be too much...

Anyway, R600, R7xx and R8xx are 4:1, but in fact R7xx lowered the ratio for some situations (less capable TMUs, half FP16 rate), R8xx lowered it again (by moving interpolation to SPs)...

I'd say R8xx in fact _increased_ the ratio slightly effectively by moving interpolation to SPs, as that eats into your ALU resources, not TEX resources.

 

[no-X]

I think we mean the same thing (it was 4:1, interpolation ate some aritmetics, available ratio remains 3.5:1 -> it was effectively decreased)

 

[mczak]

I think we mean the same thing (it was 4:1, interpolation ate some aritmetics, available ratio remains 3.5:1 -> it was effectively decreased)

Ok. You wrote though it was decreased for both rv7xx and rv8xx which isn't true (rv7xx increased the ratio by a factor of 2 in theory for fp16).

 

[Vincent]

My bet on RV9XX--

Faster L2 Cache Speed and Cache Coherence.

Better Utilization of SIMDs

384bit/256bit

 

[rpg.314]

My bet on RV9XX--

Faster L2 Cache Speed and Cache Coherence.

Yup.

Better Utilization of SIMDs

Yup.

384bit/256bit

Nopes/yup.

:smile:

Come to think of it, if amd had wafers for NI at CES, they could very well do a silicon respin before they launch it in H2.

Dirk Mayer said the entire lineup will be refreshed in H2. It will be a slaughter if the new parts arrive by say, Aug/Sept.

 

[Ailuros]

Considering Cypress is 20, how would that work?

20*16; I was referring to the latter and not the former

If I haven't understood fellix wrong he's proposing 16*32.

 

[rpg.314]

20*16; I was referring to the latter and not the former

If I haven't understood fellix wrong he's proposing 16*32.

I think he's proposing 32*16.

 

[Vincent]

I think he's proposing 32*16.

32*16 is too big for real adavanced architecture.

 

[Ailuros]

I think he's proposing 32*16.

Me dimbass didn't think of that. Theoretically should work fine.

 

[rpg.314]

Me dimbass didn't think of that. Theoretically should work fine.

I only meant that fellix was suggesting to keep the simd organization the same (efficiency tweaks aside), just increase the simd count by 60%.

 

[Ailuros]

I only meant that fellix was suggesting to keep the simd organization the same (efficiency tweaks aside), just increase the simd count by 60%.

I understood what you meant. When fellix said 32 SIMD I didn't think of them as clusters but SIMDs in the other sense. And as I said I guess as an idea it could work (even more so under the speculative light that they might again go with parallel development like Cypress/Juniper) but it doesn't suggest any significant architectural change on first sight.

 

[no-X]

mczak: Yes, you are right for R6xx->R7xx, thanks!

 

[MarkoIt]

Is anybody considering N.I at 40nm?
It makes more sense to me to launch a new architecture with a well know m.p. They won't launch an entire line up at 28nm , even if it's "just" a RV9xx and not a new architecture. They need a "pipe cleaner " first, and i don't see it coming before the end of 2010. To me, it makes more sense for ATI launching a new architecture at 40nm by the august/sept. of 2010, a pipecleaner mid-market refresh (like RV740) at 28nm in Q1 2011, and than the second iteration of N.I architecture at 28nm in June 2011.
Considering that ATi with Cypress was trying to achieve twice the performance of RV770 and they achieved just 50-60% more, there is a lot of space for a new architecture to catch up with efficiency.
And I don't think Nvidia will be able to launch something at 28nm before mid 2011.

 

[Bouncing Zabaglione Bros.]

Come to think of it, if amd had wafers for NI at CES, they could very well do a silicon respin before they launch it in H2.

Dirk Mayer said the entire lineup will be refreshed in H2. It will be a slaughter if the new parts arrive by say, Aug/Sept.

I expect AMD to target Aug/Sept as the back to school and leading to Christmas time for the OEMs, much as they did last year. I can't see Nvidia producing anything up to date and attractive for OEMs in the mass market if all they've got it a respin of Fermi or yet another rebadge of a three year old chip. Fermi is too big, expensive and overpowered for the mass market, and so leaves the way open for any mainstream parts from AMD. The lower Nvidia parts are not DX11.

 

[tannat]

I'm aware that this is not going to happen (NWIH) but it will have to happen sooner or later for a future generation:

Let's say that NI was done on SOI. The main advantages I would guess would be decreased parasitic capacitance and better thermal envelope. (I'm a III-V SC guy, so I may miss on the main advantages here).

This would probably mean that the chip would be able to raech quite much higher clocks. Has anyone any idea on what ratio SoI would give?

What was achieved when did CPUS did go SOI, and when was that?

 

[rpg.314]

I'm aware that this is not going to happen (NWIH) but it will have to happen sooner or later for a future generation:

Let's say that NI was done on SOI. The main advantages I would guess would be decreased parasitic capacitance and better thermal envelope. (I'm a III-V SC guy, so I may miss on the main advantages here).

This would probably mean that the chip would be able to raech quite much higher clocks. Has anyone any idea on what ratio SoI would give?

What was achieved when did CPUS did go SOI, and when was that?

NI is 28nm bulk. AMD's discrete gpu's will stay on bulk processes.

 

[tannat]

NI is 28nm bulk. AMD's discrete gpu's will stay on bulk processes.

I know, but at one point or another gpu functionality, at least for low end gpu power, will have to move to SOI. Fusion is not that far away.

Is it out of the box to think that graphic functionality will come from NI architecture?