AMD: R9xx Speculation

[rpg.314]

Hmm... I wonder about this Hecatonchires chip, if it exist and if the name could be indicative of something in the architecture, it could be that the SIMD could be changed in order to accomodate 100SP per SIMD instead of 80 (hekaton=100). This way, the ALU:TEX goes to 5:1 and you could have more math per SIMD with the increase in die area being not so big. I wonder if with the process improvements and reengineering the die size could be actually the same as Cypress. This way, with 20 SIMDS, you have 2000 SP, or a 25% increase in the SP count.
Or , it could be simply 4890 anew, that is, a Cypress-like chip aimed for 1 GHz frequencies

Here is a company which switched from the RV8xx->Evergreen naming just to throw off track all the curious onlookers. You reckon they'll let anything besides fud leak thru from a code name?

 

[rpg.314]

For what it's worth I think the sweet-spot strategy consists of reducing risk by being conservative on node transitions, hence RV670 on 55nm (early days for sweet-spot) and RV870 on 40nm.

The in-between GPUs, at "1 year intervals" then go to the max with new stuff: RV770 and, in my opinion, Hecatoncheires. This is relatively safe, because there is no node transition - TSMC has recently decided to ditch optical shrink half-nodes.

So, the way I see things playing out, Hecatoncheires will be a considerably bigger version of Cypress, with new design concepts, improved performance but maybe no increase in unit counts.

28nm seems like it has been roadmapped for the end of 2010 for a while - i.e. TSMC is basically saying its schedule has not been affected by the 40nm fuck-up.

Logically the first chip on 28nm should be something like Hecatoncheires with a few less SIMDs, half the ROPs and 128-bit memory bus. Scaling from 40nm to 28nm is, technically 49%. That's even more than 55nm->40nm. In truth, well...

Anyway, if AMD builds a 150mm² chip on 28nm for 2010Q4/2011Q1, it would be like RV740 all over again, pipe-cleaning. And pretty fast.

Jawed

Makes sense overall, but doesn't it make Hecaton's life too small? If 28 nm is not fucked up, then NI could possibly come out less than a year into Hecaton's life.

 

[Jawed]

Makes sense overall, but doesn't it make Hecaton's life too small? If 28 nm is not fucked up, then NI could possibly come out less than a year into Hecaton's life.

What defines NI?

I'm suggesting that NI might be the same design as Evergreen+ (the first of which is Hecatoncheires, unless that is a family name , in which case that family), merely shrunk to 28nm. Maybe with a few tweaks. 28nm is a major node, i.e. high-risk.

It seems to me AMD is set to chip away at its GPUs now, instead of doing "big bangs" like R600 or Fermi. G80 was the last successful big bang.

The APU concept is meant to get an annual refresh. That's a timetable that isn't very accommodating of big bang risks, I suppose. Though BD with on-die GPU, whenever it comes, constitutes a big-bang of sorts - though not if you compare it with Llano.

Jawed

 

[neliz]

I think Hecatoncheires is not part of Northern Islands, but something distinct. i.e. H100 could be HD6000 and N.I. could be HD7000

 

[rpg.314]

AMD has the capability to reserve a wodge of L3 for HT Assist. It could also reserve a wodge of L3 for the GPU. The scale of L3 and the sharing of the GPU by all cores, seems to make L3 the best place for CPU<->GPU coordination.

The middle ground you're apparently proposing just seems to be no-man's land.

On second thoughts, you are prolly right.

The latter is OpenCL, the former is, well I dunno, seriously more tricky. Larrabee does this by uber-tight integration (which I like, and I think it is what you're actually looking for).

LRB1 does this by reducing a decade and half's worth of investment in GPU's to yet-another-ISA-extension. Fucking ugly. The closest to system level programmability so far has been Cell. It has PPE<->mailboxes to send messages, but (on surface atleast) it seems more suitable to non-evovling architectures like consoles. Dunno what can be it's equivalent in sending bits of data out to gpu kernels or vice versa.

 

[eastmen]

What defines NI?

I'm suggesting that NI might be the same design as Evergreen+ (the first of which is Hecatoncheires, unless that is a family name , in which case that family), merely shrunk to 28nm. Maybe with a few tweaks. 28nm is a major node, i.e. high-risk.

It seems to me AMD is set to chip away at its GPUs now, instead of doing "big bangs" like R600 or Fermi. G80 was the last successful big bang.

The APU concept is meant to get an annual refresh. That's a timetable that isn't very accommodating of big bang risks, I suppose. Though BD with on-die GPU, whenever it comes, constitutes a big-bang of sorts - though not if you compare it with Llano.

Jawed

I still believe that Hecatoncheires (seriously wtf is with the name, it should be simple and short like cypress or something this is why people like r600 , g80 and so on) is just a die shrunk cypress with mabye a few enhancments and mabye more shaders.

Sinceits on 28nm it should be up to 40% smaller than the cypress on 40nm. They can use it not as a pipe cleaning part but to move cypress and the rest of ati's 40nm dx 11 chips into lower price points while NI will come towards the end of the year and be the brand new gpu by ati .

Makes sense to me because the 28nm cypress will let them demand high prices on boards that cost alot less. If fermi isn't what its cracked up to be and the current ati line up is competetive then the 28nm cypress should slot into the same price or slightly lower while being much cheaper to produce.

NI then can take over for the 5970 and demand even larger prices because the performace should be greater than a 40nm fermi or else ati messed up.

 

[CarstenS]

At least Hecatoncheires is epic! And evil and chaotic. Plus, it has electric immunity, which should be nice for overvolting. It cannot attack with all hands simultaneously, though - which we've already come to know and love from Atis 5-way ALUs. It's also extraplanar, meaning: Not from this world i guess.
[L'INQ]

So sorry, but I couldn't resist.

On a more serious note: There were THREE of the hecathoncheires. Sweet-Spot-Executed, Salvage plus Dual-GPU?

 

[leoneazzurro]

Here is a company which switched from the RV8xx->Evergreen naming just to throw off track all the curious onlookers. You reckon they'll let anything besides fud leak thru from a code name?

Probably, I used a lot of "if" in my post

 

[Jawed]

http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=223100614

Chiang: ''The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year, and followed by three months later December will be the 28 HPL. This is the first high-k metal gate introduction for the low power application.
[...]
Chiang: ''Going forward, we plan to introduce 22 nanometer node about two years after we introduce 28 nanometer, so the first introduction we'd like to be in the Q3 of 2012, and this if for the high performance version. And followed by the low power version about the end of Q1 2013.

And for light relief:

I was shocked to sign a P.O. only couple weeks ago shortly before my vacation. I signed a 1.9 million euro purchase order for a clamp.

This clamp is a custom made clamp only for EUV. We have to mount a special clamp on the ceiling and this clamp will be used to lift the EUV tool when we install the machine, and when we do the maintenance. This tool is so heavy, no other tool can lift it up, and this custom-made clamp costs us 1.9 million euros, just to buy a clamp. It's really shocking.

Jawed

 

[MfA]

Man, 22 nm schedules are looking fucking shaky IMO. That they are even still seriously talking about maskless is scary (never going to fly on the same scale as present techniques unless they can scale to millions of simultaneous beams, which I don't think they can). It's EUV or nothing at the moment ... the multi-beam ebeam writers are nice, for making masks faster ... but nothing more.

 

[rpg.314]

A half node shrink (28nm->22nm) taking 2 years, that is if it all works out. Is this the beginning of the end of Moore's Law?

AFAIU, below 22nm, all bets are off. Is that correct?

 

[MfA]

Well Intel is going far below 22 nm even without EUV, but they are doing it with multipatterning ... an approach which TSMC isn't even hinting at.

 

[itsmydamnation]

A half node shrink (28nm->22nm) taking 2 years, that is if it all works out. Is this the beginning of the end of Moore's Law?

AFAIU, below 22nm, all bets are off. Is that correct?

22nm if a full node, 28 is the half of 32nm.

cheers

 

[hoom]

A half node shrink (28nm->22nm) taking 2 years

I thought 45, 32 & 22nm are full nodes & 40 + 28nm are half nodes?

 

[rpg.314]

I meant half node as in half of the 0.707 scaling (whether from 45->40 or 40->32)

TSMC has needed typically a year to do a half node shrink.

 

[Jawed]

http://danielnenni.com/2010/02/28/tsmc-vs-globalfoundries-vs-ibm/

 

[FrameBuffer]

http://danielnenni.com/2010/02/28/tsmc-vs-globalfoundries-vs-ibm/

unless I missed something (and I may have) that article is mislabeled.. it's hardly a run down of TSMC v. GF v. IBM and more of a general summary of TSMCs proposed plans with a 1 sentence referring to IBM and GF in comparison at the end.

Almost looks like a marketing junket put out as saying "Hey we are still here.. over HERE.. HEY ME!" and EUV sounds promising it's actual performance remains to be seen.

Edit: not shooting the messenger (Jawed) by any means.. just my humble opinion.

 

[rpg.314]

NI wafershots??

At least one of the wafers contained AMD/ATI GPUs.

 

[Vincent]

unless I missed something (and I may have) that article is mislabeled.. it's hardly a run down of TSMC v. GF v. IBM and more of a general summary of TSMCs proposed plans with a 1 sentence referring to IBM and GF in comparison at the end.

Almost looks like a marketing junket put out as saying "Hey we are still here.. over HERE.. HEY ME!" and EUV sounds promising it's actual performance remains to be seen.

Edit: not shooting the messenger (Jawed) by any means.. just my humble opinion.

IBM's foundry alliance--> GF,Samsung, Toshiba.

TSMC ( IMEC-TSMC Research Collaboration ) ---> Non IBM's foundry alliance

 

[Bouncing Zabaglione Bros.]

NI wafershots??

I wouldn't be surprised. I think ATI is going to abandon TSMC and go to GF for an aggressive move to the next process node. If they manage it, they will really pile the hurt onto Nvidia.