AMD: R9xx Speculation

[Shtal]

Hi!

This might be true that ATI R9xx GPU possibly be released second half of 2010 on 28nm or 32nm, right here press release from http://www.globalfoundries.com/newsroom/2009/20090930_GSA.aspx dated back September 30th, 2009 - it talks about that volume production of 32-nm super high performance process (SOI+HKMG) will begin in 2H 2010, while volume production of 28-nm high performance process (HKMG) will as well start in 2H 2010. Here is another http://www.globalfoundries.com/newsroom/2010/20100215.aspx it says how high-end ARM designs will be out in 2H 2010 using both Global foundries' 28-nm high performance HKMG and 28-nm super low power HKMG process nodes. So, it looks like it is defiantly is entirely feasible for ATI to launch the "Northern Islands" generation on Global foundries 28-nm process this year; no doubt supplies will be constrained for first few months, but it wouldn't be any worse than what ATI went through last year with TSMC's 40-nm process.

 

[Tahir2]

I thought GloFlo and TSMC are going straight to 28nm?

 

[dizietsma]

I wonder if moving to GF is a result of the problems with the problems with 40nm from Taiwan fab? Mind you AMD when it owned the foundry didn't have massive success going to new process nodes, 65nm for instance....

 

[rpg.314]

http://www.semiaccurate.com/forums/showpost.php?p=29245&postcount=33


So sometime October, November then? I wonder how many chips are coming in 2010.

 

[Shtal]

ATI's next gen DX11 chip is 40nm http://www.fudzilla.com/content/view/17782/1/

I don't believe Northern Islands will be on 40nm since it will increase die size and it is against their "sweet spot" policy.

 

[rpg.314]

If fudo is right, then may be NI is Evergreen+2.

But then it flies in the face of what Charlie is claiming and what Anand said.

All in all, the only known is that some new chips are coming later this year.

 

[Mindfury]

Maybe ATI will try new architecture on 40nm,make a chip slightly bigger than Cypress.When 28nm is ready,double everything to make a monster chip.

 

[Silent_Buddha]

"Lurkermode off"

What if Ati has been quite happy with being first to the table with HD5xxx and 40 nm in spite of the problems of TSCM. They are not that afraid of (and quite good at) being early adopters to a smaller process node.

It has several advantages:

1) They can be agressive while playing safe by double up with GF and TSCM making two layouts for the chip. Minimizing risks of a repeat of the problematic 40 nm adoption.

2)Whatever first fab ready with 28 nm out makes launch date. If glofo is delayed TSCM may come through and vv

3) If TSCM and glofo are ready quite simultaneously there will be less constraints of cards at launch since two 28 nm lines are used to satisfy demand. Even if early cypress yields wer low, say in 30-40% Ati may have realized that one line operating att 90% yield would not have been enough for early demand.

This could have been clear while still in negotiation with TSCM and glofo about NI. They just went for both.

Well HD 58xx (Cypress) benefitted from the experience they had on 40 nm with Rv740. That allowed them to avoid many of the problems that Rv740 ran into (going by Anandtech's article), thus allowing Cypress to have less problems than they might otherwise have had.

I'd believe the 28 nm for N.I. more if ATI releases something before then to "test" the process first to see if there's any unexpected problems they might run into, and thus allow them to better adjust N.I. for those potential problems.

Regards,
SB

 

[Squilliam]

Well HD 58xx (Cypress) benefitted from the experience they had on 40 nm with Rv740. That allowed them to avoid many of the problems that Rv740 ran into (going by Anandtech's article), thus allowing Cypress to have less problems than they might otherwise have had.

I'd believe the 28 nm for N.I. more if ATI releases something before then to "test" the process first to see if there's any unexpected problems they might run into, and thus allow them to better adjust N.I. for those potential problems.

Regards,
SB

Wouldn't it be more practical to switch foundries with a new chip than it would be productive to simply port a chip from one to the other? Also theres the thing that they don't want to telegraph their intentions to Nvidia/TSMC whom both have a lot to lose in an effective transition. If they have a lot of leeway in terms of time it seems to make sense for them to jump in with both feet and work it out later if they know they have plenty of time before TSMC makes the switch (as they should as a client of both). Thats the flip side to what you wrote. Im a chronic contradictor, whats a GPU?

 

[eastmen]

Well HD 58xx (Cypress) benefitted from the experience they had on 40 nm with Rv740. That allowed them to avoid many of the problems that Rv740 ran into (going by Anandtech's article), thus allowing Cypress to have less problems than they might otherwise have had.

I'd believe the 28 nm for N.I. more if ATI releases something before then to "test" the process first to see if there's any unexpected problems they might run into, and thus allow them to better adjust N.I. for those potential problems.

Regards,
SB

For all we know N.I may have already tapped out and they may be testing it already. I'm going to think they know alot more about GF's processes than TMSC's.

Mabye the first chip we will see is early summer cypress on 28nm to test the waters. They'd be able to up the clocks while lowing power , most likely be able to refresh the 5970 also. 1.2ghz on a 5890 and 1ghz on a 5990 would be a good refresh product .

 

[Silent_Buddha]

Wouldn't it be more practical to switch foundries with a new chip than it would be productive to simply port a chip from one to the other? Also theres the thing that they don't want to telegraph their intentions to Nvidia/TSMC whom both have a lot to lose in an effective transition. If they have a lot of leeway in terms of time it seems to make sense for them to jump in with both feet and work it out later if they know they have plenty of time before TSMC makes the switch (as they should as a client of both). Thats the flip side to what you wrote. Im a chronic contradictor, whats a GPU?

Switching your entire new line would be extremely risky if you have nothing prior to indicate whether the transition will go well or go horribly or anything in between.

Add to that if 28 nm is delayed for some reason, you've basically blown an entire product cycle. The potential to have a longer delay than Fermi would be great.

Then again, with high risk there's also high reward. If it does go smoothly, 28 nm would be a huge advantage (in theory). Just like if 40nm had gone well with Fermi, it would have been a huge counter to Cypress.

But really, it's like an all or nothing bet without something to show its viability or expose any problems. Not to mention crossing your fingers and hoping the process node doesn't get delayed.

Regards,
SB

 

[tannat]

Well HD 58xx (Cypress) benefitted from the experience they had on 40 nm with Rv740. That allowed them to avoid many of the problems that Rv740 ran into (going by Anandtech's article), thus allowing Cypress to have less problems than they might otherwise have had.

I'd believe the 28 nm for N.I. more if ATI releases something before then to "test" the process first to see if there's any unexpected problems they might run into, and thus allow them to better adjust N.I. for those potential problems.

Regards,
SB

Yes, a Rv8xx chip on 28 nm would be a strong indication of 28 nm.

Going GloFo and TSMC in parallel may be additionally rewarding if they want to continue launch several die size versions within a short time frame as with Rv8xx.

It would also be an incentive for TSMC to be on the toes and not be sloppy with tool calibrations. Also, if Ati go through the effort of making separate layouts and prework on both companies 28 nm processes, then SoI on GloFo and bulk Si on TSMC may not be a huge additional step.

Rv8xx has been quite successful, this double approach may possibly mitigate most problems seen with Rv8xx launch with while enabling Ati to jump on the new node for next architecture safely.

 

[neliz]

the next RV8xx will still be on 40nm and the chances that RV9xx will go to GloFo seem to be slim.

 

[Psycho]

"The next RV8xx"?

 

[neliz]

"The next RV8xx"?

Hecatoncheires, the RV8xx refresh. i.e the part nv doesn't compare GF100 to when they claim "worlds fastest graphics solution."

 

[Bouncing Zabaglione Bros.]

NI on GF sounds to me like a bold move, and while it does seem to be a little like wish fulfilment, it does seem like a more radical management move ie the kind of thing we've seen from ATI over the last couple of years, with early moves to gain process advantages.

If you do consider R8xx to be an evolved version of the previous generation, then that would mean a more serious redesign is due, and maybe ATI think they need a next-gen process to do it. It the sort of reason why ATI and AMD merged in the first place. A move to a new architecture on a new process under the auspices of GF may be potentially risky, but it also has the potential to be massively rewarding, and I think it's just the sort of challenge that the current ATI will take on.

 

[leoneazzurro]

Hmm... I wonder about this Hecatonchires chip, if it exist and if the name could be indicative of something in the architecture, it could be that the SIMD could be changed in order to accomodate 100SP per SIMD instead of 80 (hekaton=100). This way, the ALU:TEX goes to 5:1 and you could have more math per SIMD with the increase in die area being not so big. I wonder if with the process improvements and reengineering the die size could be actually the same as Cypress. This way, with 20 SIMDS, you have 2000 SP, or a 25% increase in the SP count.
Or , it could be simply 4890 anew, that is, a Cypress-like chip aimed for 1 GHz frequencies

 

[mboeller]

The Hecatonchires,
or Hekatonkheires (pronounced /ˌhɛkətɒnˈkaɪriːz/; Greek: Ἑκατόγχειρες ( (listen) (help·info) "Hundred-Handed Ones," Latinized Centimani), were figures in an archaic stage of Greek mythology, three giants of incredible strength and ferocity, even superior to that of the Titans whom they helped overthrow. Their name derives from the Greek ἑκατόν (hekaton; "hundred") and χείρ (kheir; "hand"), "each of them having a hundred hands and fifty heads" (Bibliotheca). Hesiod's Theogony (624, 639, 714, 734–35) reports that the three Hecatonchires became the guards of the gates of Tartarus.

http://en.wikipedia.org/wiki/Hecatonchires

Multithreading ?? ??

 

[Jawed]

For what it's worth I think the sweet-spot strategy consists of reducing risk by being conservative on node transitions, hence RV670 on 55nm (early days for sweet-spot) and RV870 on 40nm.

The in-between GPUs, at "1 year intervals" then go to the max with new stuff: RV770 and, in my opinion, Hecatoncheires. This is relatively safe, because there is no node transition - TSMC has recently decided to ditch optical shrink half-nodes.

So, the way I see things playing out, Hecatoncheires will be a considerably bigger version of Cypress, with new design concepts, improved performance but maybe no increase in unit counts.

28nm seems like it has been roadmapped for the end of 2010 for a while - i.e. TSMC is basically saying its schedule has not been affected by the 40nm fuck-up.

Logically the first chip on 28nm should be something like Hecatoncheires with a few less SIMDs, half the ROPs and 128-bit memory bus. Scaling from 40nm to 28nm is, technically 49%. That's even more than 55nm->40nm. In truth, well...

Anyway, if AMD builds a 150mm² chip on 28nm for 2010Q4/2011Q1, it would be like RV740 all over again, pipe-cleaning. And pretty fast.

Jawed

 

[Jawed]

Yeah, the gpu will eat up the L2. But if you share via L3, it'll eat up L3 too.

L3 is ~10x bigger than an L2.

Also, the on-die GPU will be eating off-die memory bandwidth. Want to keep that traffic away from module L2

The only way out seems to be to put an upper limit on the amount of cache the gpu can hog. And if you are gonna cap L3 usage, might as well put it together with a module and cap L2 uage as well.

AMD has the capability to reserve a wodge of L3 for HT Assist. It could also reserve a wodge of L3 for the GPU. The scale of L3 and the sharing of the GPU by all cores, seems to make L3 the best place for CPU<->GPU coordination.

The overall direction is to make it system level programmable, instead of using the gpu as a device visible to apps.

The latter is OpenCL, the former is, well I dunno, seriously more tricky. Larrabee does this by uber-tight integration (which I like, and I think it is what you're actually looking for). The middle ground you're apparently proposing just seems to be no-man's land.

Jawed