chavvdarrr
Veteran
and I see "4" for Cayman RPEs :S
Still TMU/Rops look like double digit.
AMD: R9xx Speculation
- Thread starter Lukfi
- Start date
Still TMU/Rops look like double digit.
I agree that looks like a 640 to me. That could be a 500mm2 chip if so, and I don't know if AMD would go there again (esp not with a ring bus
).
That's a clear 3 IMO.
Gah, should just fire up PhotoShop and figure out which kinda blur they've used.
I agree that looks like a 640 to me. That could be a 500mm2 chip if so, and I don't know if AMD would go there again (esp not with a ring bus
The thing is 480 stream processors is only ~33% larger than Barts and it is also quite likely that with it being a larger chip it won't clock as high so all things being considered there probably wouldn't be much difference between the two.
I know I could and am probably wrong!
Anyway, whats the chances they have developed an architecture which decouples the TMU quantity from the ROP and Stream processor SIMD count?
Wasn't R600 exactly like that? TMUs were separated by SP SIMDs and could be used by any SP SIMD?
I' am confident that ATI/AMD will not go over 400mm2 die size.
Specs like, 480(X4) processors, 48 ROP's, 96TMU's and 30 SIMD's...... Looks more legit.
Cayman 640(X3) or 640(X4) processors will be as big as Nvidia Fermi GPU over 500mm2
AMD should / will avoid building such large chip. "AMD will NOT be like Nvidia".
Specs like, 480(X4) processors, 48 ROP's, 96TMU's and 30 SIMD's...... Looks more legit.
Cayman 640(X3) or 640(X4) processors will be as big as Nvidia Fermi GPU over 500mm2
AMD should / will avoid building such large chip. "AMD will NOT be like Nvidia".
Looking at old bench test here for ATI 6870 http://www.google.com/imgres?imgurl...mages?q=ati+6870+gpu-z&hl=en&gbv=2&tbs=isch:1
Default clocking GPU @ 850MHz clearly tells me such high clock speed GPU will NOT be over 400mm2.
EDIT: To keep Cayman GPU under 200W TDP with high clock speed ONLY be possible with smaller die size.
Default clocking GPU @ 850MHz clearly tells me such high clock speed GPU will NOT be over 400mm2.
EDIT: To keep Cayman GPU under 200W TDP with high clock speed ONLY be possible with smaller die size.
Last edited by a moderator:
UniversalTruth
Veteran
No, 2560 SPs will not result in such a big chip, over 500 mm2. I don't know where your estimations come from.
I am sure that if Cayman comes with 1920 activated SPs, it doesn't necessarily mean that in fact it hasn't more than 2000.
You know what would be funny? If the original rumors turned out to be true, where "6700" (now Barts, 6800) would indeed be faster than a GTX480 and do 3TFlop.
and re: Die size.. don't worry!
UniversalTruth
Veteran
OMG! That wouldn't be funny, that would be great and would be a great explanation why Barts is 6800 series. I will be more than happy. It's possible to guestimate the die-size of both configuration, considering Cypress die-size and rumors.
Cypress has a die of 324 mm^2. 1/3 is the space taken by the SIMDs (info that comes from RV770). So in Cypress 108 mm^2 are taken by 1600sp. If the 25% increase space efficiency is true, than in N.I 1280 sp (320x4) can fit in 81 mm^2 and perform as the 1600sp of Cypress. Double that gives, 162 mm^2 for SIMD. A 20% of increase in complexity of the uncore/fixed function unit (TMU/rops), gives about a die-size of 420-430 mm^2 for 2560sp/96TMU/48rops and 380-390 mm^2 for 1920sp/96TMU/48 rops.
By the way, Cayman ROPs can't be 32.. because 32/3 give 10,6 rops per RPE
And the same for the SIMD number..640 can't fit 3 RPE.
Crap. You rule.
But how did HD2900GT work? It had 12 TMUs.
Jawed
Legend
You asked the right question though, as it's a useful comparison
R600 architecture matches the count of quad-ALUs per SIMD to the count of quad-TMUs, as in R6xx TMU count says nothing about ALU SIMD count. So 240 ALU lanes is 4 SIMDs each containing 3 quad VLIW-5 (60 ALU lanes per SIMD). So 3 quad-TMUs, where each quad-TMU feeds its results solely to the same numbered quad-ALU inside all 4 of the SIMDs.
Code:
TMU1 TMU2 TMU3
| | |
ALU1 ALU2 ALU3 - SIMD 1
| | |
ALU1 ALU2 ALU3 - SIMD 2
| | |
ALU1 ALU2 ALU3 - SIMD 3
| | |
ALU1 ALU2 ALU3 - SIMD 4So in that sense this new design is like R600. So the question is: what kind of bus architecture, what kind of inter-cache sharing is used, and how far do texturing results travel?
Because R6xx never exceeded 4 SIMDs, we don't know what TMU sharing arrangement would have been implemented with more SIMDs and more TMUs. e.g. it appears likely these new GPUs have TMUs localised to an RPE, whereas R600 shares them across all SIMDs.
R5xx and R6xx don't match ROPs to MCs, whereas R7xx does. R7xx therefore keeps a vast amount of bandwidth local to an MC and so it's easier to get away without a ring bus. Though in fact the internal bandwidth from L2s->L1s is ~4x higher than off-die bandwidth. Being unidirectional helps, I guess (obviously commands go the other way, but not a huge bandwidth).
There's also shader export data that needs to go to the MCs (GS export or PS export) but that's relatively low bandwidth, e.g. 32 4-byte results per clock.
Barts with 64 TMUs might only have 8 L1s, which is an improvement on the 10 of Juniper. Each L1 in this setup would be dual-ported, feeding two quad-TMUs, which obviously adds local complexity.
The other side of the bandwidth question is making read/write UAV access efficient. Global atomics are very efficient in Evergreen, but more generic operations are un-cached. Really they should be cached (this would also help register spill). The patents I've been referring to seem to hint that they will hold data written to them by SIMDs, not merely that they will hold texel data.
In the extreme it's possible they've implemented a distributed coherent read/write L1, which would make read-write UAV work really fast. L2, in this scenario, wouldn't do coherency, it merely increases efficiency of MC and ROP operations. I suppose...
While I tend to agree, there is no reason why AMD couldn't go with a 640 shader behemoth, coming in at around 50% faster than the gtx 480. They won't do it, but they could.
Impact on L1 latency?
Jawed
Legend
Probably.
I completely forgot that simd width (and hence wavefront size) could not only be varied with different chips, but actually also within a specific chip by disabling parts.
So, since that's apparently easy, wouldn't that make it more likely AMD has indeed increased wavefront size to 80, and a RPE is just 8 SIMDs, with a more traditional TMU arrangement (quad tmu per simd)? So the tmus are still local to SIMDs, and RPE just includes rasterizer plus some more stuff (tesselator plus some more).
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